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Examining structural faults that lead to glitches

Posted: 19 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:SoCs? IP? clock gating? glitch? mux?

Glitch due to reset crossing
Referring to the design of figure 4, the enable of a clock gating cell is coming from a flop which clears the enable signal asynchronously due to assertion of asynchronous reset ( Func_rst) while the input clock is still active, this can produce glitch at the output of the cell. A design solution for this is to synchronise the enable using 2-DFF structures which are either non C resettable flops or having POR as reset. This ensures that there is no asynchronous path from flop generating enable and clock gating cell.

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 Glitch due to reset crossing

Figure 4: Glitch due to reset crossing.

Other scenarios
There are other scenarios that can lead to glitches in clock. One of them being the use of combinational gates (and, nor, xor etc ) and instead of cg cells for gating of clocks (figure 5).

While using a cg cell, there might be a case where the enable is launched from a clock domain that is different from that of the clock to be gated. This may also lead to glitches in the clock. Such cases need to be carefully reviewed and fixed in design after being caught by a tool or gls.

 Using combinational gates for clock gating

Figure 5: Using combinational gates for clock gating.

Sources of data glitches
Any combinational logic used in a data path is glitch prone. But since the timing parameters are met for each and every synchronous path, the glitch will not be sampled in the destination domain. But there are cases (described below) where such timing parameters are not met and glitches may get sampled in the design.

Use of combinational logic at CDC Path

In an ideal situation, there should be no combinational logic present at the CDC Interface. If such logic is present it may lead to a glitch. Also the glitch may get sampled in the destination domain and may lead to erroneous behaviour. Here again designer needs to review all the paths at the interface. We may waive the structure shown in figure 6 if all the other inputs to this combo logic are static when used. Such structures can easily be caught with any CDC tool or in gls.

 Combinational logic at CDC Path

Figure 6: Combinational logic at CDC Path.

Glitch at converging paths through an analogue block
Referring to figure 7, we have two inputs A and B which are combined through an "and" gate and fed to analogue IP. There is also another "and" gate which has B and the output of an analogue IP as inputs. The output of the second "and" gate is fed back to the analogue IP. Consider a case where B toggles and A = 1 we may observe glitches at the output of the second "and" gate. This kind of design which is purely combinational (with some hard macros) is always glitch prone. The glitch may get sampled in the design and may lead to unexpected behaviour. Such cases need the attention of designer and needs to be fixed in design.

 Glitch at converging paths through analogue block

Figure 7: Glitch at converging paths through analogue block.

It is very important to make our design free of any clock or data glitches to ensure correct functioning of the design. There are cases where such issues have not only caused functional failure but increased execution cycle time by adding some extra debug time and effort. Hence it is very important for a designer to take care of such issues at very early stage of design once flagged by tool or gls.

About the author
Ankush Sethi is design engineer at Freescale Semiconductor India Pvt Ltd.


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