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LPDDR4 verification IP speeds up verification sign-off

Posted: 11 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? verification IP? LPDDR4? UVM? memory controller?

Synopsys Inc. has brought to market its JEDEC LPDDR4 verification IP (VIP) based on a 100 per cent native SystemVerilog Universal Verification Methodology (UVM) architecture. According to the company, the solution promises to enable ease of use, ease of integration and performance with regard to high-performance, low-power designs.

Complete with verification plans, built-in coverage and a protocol-aware memory debug environment, Verdi protocol analyser, Synopsys VIP for LPDDR4 is a complete VIP solution that speeds up verification sign-off for designers of low power memory controllers and SoCs.

The VIP includes transactor and monitor functions to provide a comprehensive set of protocol, methodology, verification and productivity features, allowing users to achieve rapid verification convergence on LPDDR4-based designs. In addition to providing LPDDR protocol verification, the Synopsys LPDDR4 VIP can be dynamically configured to model any memory vendor component without the need to recompile, enabling SoC teams to rapidly verify the range of components that will be used with their SoCs.

Synopsys VIP for LPDDR4 is available standalone and as part of the Synopsys VIP Library and the Verification Compiler product. The LPDDR4 VIP is also included as part of Synopsys' complete DesignWare IP solution for LPDDR4 that includes controllers, PHY and VIP.





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