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Cadence platform boasts notable increase in SoC verification

Posted: 15 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? SoC verification? UML? FPGA? HDL?

Cadence Design Systems Inc. has uncloaked the Perspec System Verifier platform for use-case scenario-based software-driven SoC verification. A part of the Cadence System Development Suite, the solution promises to cut complex test development from weeks to days, while also allowing design teams to reproduce, find and fix complex bugs to enhance overall SoC quality, the company indicated.

Using an intuitive graphical specification of system-level verification scenarios and a definition of the SoC topology and actions, the verification solution automates system-level coverage-driven test development using constraint-solving technology, delivering up to 10x productivity improvement in SoC verification versus typical manual test development, stated Cadence.

The Perspec System Verifier offers a Unified Modelling Language (UML)-based view of system-level actions and resources which, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions. It also features a solver technology that automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios to verify SoC-level features for functionality, performance and power. It also accommodates tests that run on all pre-silicon verification platforms including simulation, acceleration and emulation, and virtual and FPGA prototyping, which can be further used to validate actual silicon.

Perspec System Verifier platform

The platform is portable, supporting reuse across SoC scope, from IP to the system level, including software; platforms including FPGAs, emulators, hardware description language (HDL) simulators, virtual platforms and silicon; and allows generated tests to be run on all Cadence System Development Suite platforms. The solution is intended for architects, hardware developers, verification engineers and software test engineers.

A part of the Cadence System Development Suite, Perspec System Verifier brings a formal, systematic, and automated approach to developing system use cases. With a Unified Modelling Language- (UML-) based view of system-level actions and resources and powerful solver technology, the platform provides an intuitive view of complex, hard-to-test system-level use case interactions.

The Perspec System Verifier enables automation, which reduces manual effort and also provides complex tests that wouldn't be written manually. It also offers abstraction and ease of use, specifying system-level scenarios in an intuitive, flexible GUI that doesn't require you to be an expert of the details of the system.

The solution offers platform support, with a reuse model and tests that work across pre-silicon and post-silicon platforms, and enables completeness of measurement, with coverage of functionality, flows and dependencies. In addition, the Perspec System Verifier delivers knowledge transfer, since the formal, model-based system description supports knowledge sharing between different groups, stated Cadence.

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