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Renesas touts soft error-free, low-power SRAM devices

Posted: 15 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Renesas Electronics? SRAM? soft error? CMOS?

Renesas Electronics Corp. has announced five additional products in the RMLV0816B and RMLV0808B series of Advanced Low-Power SRAM (Advanced LP SRAM), the company's flagship SRAM devices. The memory devices boast a density of 8Mb and use a fine fabrication process technology with a circuit linewidth of 110nm, detailed the company.

According to Renesas, the devices are high-reliability products that achieve the same soft error rate as Renesas' earlier products that were fabricated in a 150nm process. They also achieve low-power operation with a standby current of maximum of 2uA at 25°C, making them suitable for data storage in battery-backup devices.

RMLV08

Renesas' low-power SRAM products are used extensively in a range of products including industrial, office automation, communication, automotive and consumer applications. As in the past, along with increased performance and functionality in user systems, the reliability of the system as a whole is critically important. This is why high reliability is required in the SRAM, which stores important information such as the system software and data. In particular, measures to deal with soft errors due to alpha rays and neutrons in cosmic radiation are seen as critical.

Since Renesas has added a capacitor to the memory node in the cell of the Advanced LP SRAM devices, these devices have an extremely high resistance to soft errors. The Renesas Advanced LP SRAM adopts structural measures that suppress soft error occurrence itself. The results of system soft error testing in Renesas' mass produced 150nm process Advanced LP SRAM has shown that these devices are essentially soft error free, stated the company.

Additionally, the load transistors (p channel) in the SRAM cell are formed as polysilicon TFT devices, and since they are stacked in the upper layer of the n-channel MOS transistors that are formed on the silicon substrate, only n-channel transistors are formed on the underlying silicon substrate. As a result, there are no parasitic thyristor structures in the memory area and thus these devices have a structure in which latch-up cannot, in principle, occur.

As a result of these design aspects, the products tout extremely high reliability compared to full CMOS type devices that have the ordinary memory cell structure. Thus they can contribute to even higher performance and reliability in equipment that requires high reliability, such as factory automation equipment, test equipment, smart grid related equipment and transportation systems.

Furthermore, Renesas Advanced LP SRAM achieves an even more compact cell size by combining polysilicon TFT stacking technology with stacked transistor technology. For example, the cell size in Renesas' 110nm Advanced LP SRAM is comparable to that in a full CMOS type SRAM fabricated in a 65nm process.

Samples of Renesas' SRAMs will be available in December 2014, priced at $11.0. Mass production is scheduled to begin in January 2015.





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