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Designing test tools to accommodate denser memories

Posted: 15 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Teledyne LeCroy? test tool? verification? JEDEC? DDR4?

Existing memory specifications and emerging memories that are denser are giving test vendors a bit of a challenge. In fact, customers are now looking for solutions that offer quick verification and this where test companies should focus on.

Bob Mart, Teledyne LeCroy's oscilloscopes product manager, said customers are looking for test tools that enable them to "hook up signals and go" so they can validate memories quickly. They also don't have the expertise internally to understand every single specification, including those from JEDEC, he added. "Oscilloscope users are not experts on the JEDEC specifications themselves."

Teledyne LeCroy recently announced its Kibra 480 Compliance Analyser aimed at helping DDR memory developers, implementers and integrators verify and validate that their DDR memory design meets JEDEC compliance parameters. Mart expects DDR4 will definitely be a busy area of focus for testing in 2015.

Most recently, Teledyne LeCroy released its DDR debug toolkit, which includes test, debug and analysis tools for the entire DDR design cycle, and is not aimed at addressing JEDEC compliance, said Mart, as many customers are integrators buying qualified memory and controllers and inserting them into their own designs and want to make sure the layout of their boards don't affect interoperability. The toolkit supports DDR2/3/4 and LPDDR2/3, and the company plans to support LPDDR4 in the near future, which Mart said will present a challenge because of its many additional features over its predecessor.

Tektronix also sees DDR4 testing gaining momentum, said Christopher Loberg, senior technical marketing manager for performance instruments at Tektronix, both this year and into 2015, as it starts to get traction in the server segment. He said once specifications for newer memory are solidified and become the defacto standard, it increases the need for quick, automated testing.

Testing solutions need to be ready for LPDDR4

Loberg said LPDDR4 is also likely to pick up steam as well, fuelled by the performance needs and power saving requirements of mobile devices, and this adds further complexity to testing. In September, the company announced a complete PHY layer and conformance test solution for JEDEC LPDDR4.

Loberg said Tektronix fields a lot of questions from designers on probing and how to manage signal integrity when testing memory for mobile devices, as architectures are designed for lower power states when the device is in hibernation but then experiences as state of "bursty" data when in use again. "The variation is challenging," he said, as probing can inadvertently draw power when the device is in sleep mode.

Denser memories also make access a challenge, said Loberg, and sometimes physically impossible, and this is where interposers come into play. Tektronix collaborates with Nexus Technologies to provide a LPDDR4 memory component interposer. Using a method called de-embedding, a physical board is used between the DRAM and the bus, which allows designers to pick up signal traffic and place it on cable or probe back to a scope.

The trend of process technology going below 20nm and 16nm presents test challenges not encountered in more mature technologies, said Bassilios Petrakis, product marketing director for Encounter Test Products at Cadence, as the type of faults are different so new algorithms are required for testing.

Cadence provides BIST engines that encompass many predefined algorithms, said Petrakis, and different memories require different built-in self-test (BIST) engines. "A modern BIST engine must be able to supply predefined and user-defined algorithms," he said. "The ability to program a new algorithm on the fly is important at testing time."

Another trend affecting test tools is that denser memories also mean the demand for repair is higher, said Steve Pateras, product marketing director for silicon test products at Mentor so that entire chips do not have to be discarded due to faulty memory. "Repair is now the norm. There's lots of redundancy being placed in these memories."

Looking ahead to 2015, Pateras said a focus for testing will be to keep up with denser cores and emerging memories, including those on the bleeding edge.

- Gary Hilson
??EE Times

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