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Imec unveils 8bit MPU using complementary TFTs

Posted: 17 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Imec? TFT? CMOS? microprocessor? Evonik?

Imec, Holst Centre and their partner Evonik have showcased a general-purpose 8bit microprocessor developed using complementary thin-film transistors (TFTs), processed at temperatures compatible with plastic foil substrates (250°C). According to the research team, they used a hybrid technology incorporating two types of semiconductor metal-oxide for n-type TFTs and organic molecules for p-type TFTs in a CMOS microprocessor circuit operating at 2.1kHz.

Although it may look like a very low clocking speed compared to GHz-capable hard silicon, these results should be seen in the perspective of organic materials' very low charge carriers mobility and represent a huge improvement over Imec's own previous research.

8bit MPU using complementary TFTs

In an email exchange with EETimes Europe, senior principal scientist at Imec, Jan Genoe explained, "Today's speed is limited by electron mobility of the n-TFT and the hole mobility of the p-TFT. In order to improve on this, exchanging the semiconductors by better state-of-art materials and processes (e.g. n-TFT with 5-10 times larger mobility) and moving to a unipolar n-type design would increase the operating frequency between 10-100Kb/s.

"Our previous work (i.e. microprocessor running at 6Hz) was limited in performance due to the utilisation of only organic p-TFT with less performance than the one published recently. Moreover, the previous publication was limited by a unipolar p-TFT design. In the current work, we have also improved our digital standard cell library, we improved the architecture of the MPU and used a hybrid complementary technology with better performing semiconductors.

"When compared with Silicon, the lower mobility yields intrinsically a speed which is about 1000 times lower than the speed of silicon. The real speed is multiple orders lower, due to the fact that we use, on the flexible foils, design rules comparable with the design rules that Intel used back in 1971. But the object of this work is not the speed, it is low-cost realisation on flexible circuits that can be embedded in any object."

For the processor core chip (ALU), a complementary hybrid organic-oxide technology was used (p:n ratio 3:1), totalling 3504 TFTs on across a 12.018.8mm substrate.

The n-type transistors are 250C solution-processed metal-oxide TFTs with charge carrier mobility of 2 cm2/Vs while the p-type transistors are small molecule organic TFTs with mobility of up to 1 cm2/Vs. The general-purpose print-programmable instruction generator (P2ROM) is a one-time programmable ROM memory with an instruction set of 16 code lines, each line providing a 9-bit instruction defined through inkjet printing, filling dedicated ink wells with a conductive silver ink. When programmed for a specific function (averager), the 9 x 6.9mm P2ROM chip employs 852 TFTs (it employs 403 organic p-TFTs and 412 oxide n-TFTs in its un-programmed state).

Genoe added, "The chip is fully operational from 6.5V onwards. This low supply voltage (for technologies on foil) is a key merit of the complementary organic/oxide technology. As the power consumption scales with the square of the supply voltage, the downscaling of the supply voltage from 10V in the prior p-type only architecture to the current 6.5V in the more robust complementary architecture results in a very substantial gain in power consumption.

"Furthermore, even at equal supply voltage, a complementary architecture has a much lower static power consumption than a unipolar one as a consequence of reduced static leakage current. The static power consumption in our case can still be further improved by shifting the on-set voltage of the p-type transistor towards zero voltage," he concluded.

The work would need further improvements to have such MPUs operate on single flexible battery, but for now, it could run from a number of such batteries connected in series.

- Julien Happich
??EE Times Europe

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