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What's hot at IEDM 2014?

Posted: 18 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IEDM? Moore's Law? finFET? 14nm?

Intel's runs a 14nm victory lap

Intel revealed just a few new details about its 14nm process in which it is now producing its Broadwell processors. Two of the key details are that it is using "a novel sub-fin doping technique for high performance transistors... and air-gapped interconnects at performance-critical layers," the paper said.

The sub-fin doping "is achieved through solid-source doping to enable better optimisation of punch-through stopper dopants." The node's 13 copper metal levels use air gapped interconnects (shown above) "at 80nm and 160nm minimum pitch layers [at levels 4-6 to] provide a 14-17 per cent improvement in capacitance."

Intel increased its use of self-aligned double patterning for critical patterning layers to boost density. But when asked by one attendee how and where Intel uses the technique, the Intel presenter declined to answer.

Intel's 14nm

Intel claims the process has the tightest minimum gate pitch in production at 52nm and the highest drive currents yet reported for 14nm technology. The taller, skinnier 14nm finFETs stand 44nm high with a 42nm pitch, compared to 34nm high with a 60nm pitch in Intel's 22nm process.

The result is a node that maintains Intel's historical trends of increasing density and slightly improves its historical rate of reducing cost per transistor. That, the Intel presenter crowed, is Moore's Law still alive and kicking.

It was an impressive job, and one on which Intel is still working to improve yields (see below). Attendees seemed to agree, packing into the room for the talk and giving the loudest and most spontaneous round of applause I heard at IEDM.


Intel's taller, skinnier fins

 Intel's taller, skinnier fins

Intel's second-generation finFETs were built for greater density, a factor that helped the company stay on Moore's Law of decreasing cost per transistor.

Intel's finFets

Intel squeezes its SRAMs


Intel's 14nm process makes its smallest SRAM cells for cache memory ever, just one result of its device level shrinks.

14nm process

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