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What's hot at IEDM 2014?

Posted: 18 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IEDM? Moore's Law? finFET? 14nm?

Avago, Renesas test TSMC 16nm

Avago and Renesas gave the first public papers on devices built in TSMC's 16nm finFET process, presumably the initial version before the optimisations described on the previous page. Both were only test chips, highlighting the still evolving nature of the process and the size of Intel's lead in finFETs.

Avago made parts of a 28Gbit/s SerDes, and Renesas made a test SRAM and support circuit. Both said the process offered significant advantages over a planar 28nm node, but both indicated they struggled with new design issues.

The company reported its device consumed 40 per cent less power than a similarly sized part built in 28 nm technology. It also said it saw a good correlation of its simulation to its actual silicon, even though it used 2013-vintage models for the design. However, it also reported "many circuit techniques were required to mitigate undesired device characteristics."

TSMC 16nm

Renesas rather generically said its 16nm SRAM had "improved minimum operating voltage, standby leakage current and access time compared to planar bulk CMOS." However, it also complained it was difficult to optimise MOS dimensions to the minimum number of finFETs, and it saw a "strong layout-dependency effect (LDE)," described above.

DNA tweezers and carbon nanotube arrays

In one paper, a researcher from the University of Tokyo described a MEMS-based device that acts as tiny tweezers to grab a bundle of DNA molecules so they can be observed in real-time. He also described a bio motor SoC that "can distinguish normal and abnormal tau-proteins related to Alzheimer's disease."

DNA tweezers

Separately, a team from Stanford demonstrated an array of more than 100 carbon nanotubes. Besides being the most dense array of the material to date, it also supported "the highest current drive per unit layout width to date (>100A/m at 400nm channel length and 1V VDS), while simultaneously achieving high Ion/Ioff (>5,000)," according to the paper.

The demo was the first to approach the performance level needed to use carbon nanotubes to create logic circuits. The arrays "approach that of similarly-scaled and similarly-biased silicon-based field-effect transistors in production in major semiconductor foundries."

One researcher compared the process used to create the array (below) to using a rubber stamp to draw a larger picture.

Stanford


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