Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Manufacturing/Packaging
?
?
Manufacturing/Packaging??

What's hot at IEDM 2014?

Posted: 18 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:IEDM? Moore's Law? finFET? 14nm?

Novel 3D and plastic transistors

Researchers at Imec, the Holst Centre, and Evonik demoed an 8bit microprocessor made in complementary thin-film transistors (TFTs) suitable for printing on plastic foil (above).

The 2.1kHz chip can be made on an inkjet printer and programmed using its write-once/read-many instruction generator. It is geared to applications such as sensors for smart food packaging as well as radio-frequency and Near Field Communication tags and flexible displays.

Novel 3D

Separately, CEA-Leti researchers described CoolCube (below), a novel approach to using the levels of copper metal-on-chip to stack different kinds of devices on a single die. IBM and Qualcomm are helping in the project, which aims to be ready for manufacturing by 2018. It aims to support not only future CMOS scaling but open a door to novel on-chip sensors and communications.

CoolCube

Cree powers up silicon carbide

Cree

Power MOSFETs are on the rise, said Cree CTO John Palmour, in a plenary talk, noting President Obama recently christened a new power electronics research centre in North Carolina. Silicon and gallium nitride products will continue for the foreseeable future, but Palmour focused on the promise of a family of third-generation silicon-carbide devices his company has in the lab (above and below).

Long-term, the technology promises new smart-grid apps such as transformer-less power substations and electric trains that dramatically reduce size, weight and cost. "You spend a lot of gas hauling that big transformer around," said Palmour.

Palmour described a family of devices in the works, ranging from 900V to 27kV, the latter switching in less than 600ns. One challenge is packaging the devices, because "you dissipate a lot of heat in a small size," he said.

Palmour

A veteran sounds a sceptical note

 John Chen

It's hard to not be optimistic, given the breadth and depth of good hard work engineers are pouring into semiconductors. That said, veteran John Chen (above) expressed a few words of caution at a panel hosted by Applied Materials.

The former head of R&D at TSMC, now a senior technologist at Nvidia, pointed to three discontinuities on the horizon, starting with the lack of a replacement for immersion steppers, the workhorse of the industry. He also lamented rising chip costs and the lack of a consensus on when larger wafers will be ready.

  • Lithography tools cannot print the fine lines we need. Double and triple patterning increases wafer costs due to their complexity. We should have moved to 450mm wafers years ago.
  • And as for yields, the semiconductor industry is unique in that when you throw 20 per cent of your products away you are happy. We have trained ourselves that 80 to 90 per cent is good. But the cost is so high now, we can't afford to throw so many chips away.

He also expressed scepticism about claims from Mark Bohr that Intel is still delivering decreases in cost per transistor along historical trend lines.

  • I don't know if Mark has proven that is the case. Transistors used to be half the cost every generation. I don't know if that is still true. Costs are lower, but I don't know if it's nearly by half.

- Rick Merritt
??EE Times


?First Page?Previous Page 1???2???3???4???5



Article Comments - What's hot at IEDM 2014?
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top