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IBM claims PCM non-volatility not necessary

Posted: 19 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:PCM? non-volatility? IEDM? SCM? DRAM?

At the 2014 International Electron Devices Meeting (IEDM), many PCM developers might have been relieved with IBM's position downplaying the need for PCM non-volatility/data-retention. However, it was just a beginning statement.

As always the devil is in the detail, and, in this case, it was for the application of PCM (pulse-code modulation) to SCM (storage-class memory). SCM is defined as the location in a multi-processor memory hierarchy between the NAND-flash based solid-state drives (SSDs) as the system memory and the SRAM closely linked to the processors. To date, because DRAM in its SCM role is about three orders of magnitude faster than Flash, it is able to deal with the frequent fetches from the system memory and now more often occupies this space.

The problem is the growth of processor parallelism while system memory latency is remaining roughly constant. The solution to the problem of servicing the multiple fetches from system memory is to add more DRAM. This increased cost of adding more DRAM in order to maintain bandwidth is imposing an unacceptable cost burden, so this could open an opportunity for PCM.

SCM essentials for PCM?

The proposition in the paper is that for PCM in an SCM role, long-term non-volatility is not essential. However, what is essential is a long list, summarised in Figure 1, of essential developments including: a need to optimise the critical and performance limiting SET operation; low-power operation; high performance, write/erase endurance; high bit density per chip; scaling; and low cost. SCMs have low read to write ratios, so to reduce switching power dissipation between read and write operations, diodes as matrix selector devices will need to be replaced with vertical surround gate (VSG) MOSFETs, where it is claimed it should be possible to achieve a 6F2 cell size similar to that of a DRAM.

Figure 1

Equalling the DRAM is not enough, to reduce costs PCM must scale beyond DRAM and, to do that, multi-bit single cell operation beyond the two bits that has been demonstrated (although not yet commercially) will be essential. So, those two requirements must be added to the list of SCM performance essentials. In addition, it is now accepted that thermal crosstalk will be a problem below 20nm, so another refinement that must be added to the SCM essentials list is thermal barriers. (Metal nitrides are suggested as a suitable thermal isolation barrier solution.)

To support claims that PCM write/erase lifetimes of 1010 cycles should be possible, the IBM paper points to write/erase lifetime or endurance data produced in 2003. This is data that ignores the fact that until 2013, the few PCM products that have reached the commercial market in each lithographic scaling step have produced a reduction in write/erase lifetime or endurance (from 1x106 at 90nm to 1x105 cycles at 45nm). The suggestion in the paper was wear levelling as a possible solution.


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