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IBM claims PCM non-volatility not necessary

Posted: 19 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:PCM? non-volatility? IEDM? SCM? DRAM?

In the past [Ref 5] it has been reported that when TRAM devices are operated with wide DC RESET pulses, they are still able to switch from the LRS to HRS state, indicating that a melt-quench step is not required.

Whatever the mechanism, it would appear that Ge vacancies facilitate the easy movement of the Ge atoms. If the Ge fraction x in the composition GexTe1-x is less than or equal to 0.5, the device structure displays the reported switching characteristics. However, with values of x greater than 0.5 the movement of Ge is blocked and switching is not possible.

Figure 5

Examples of the operating characteristics of a TRAM are shown in Figure 5; an important differentiating feature is the existence of what is called the transitional resistance state (TRS), shown in green. This is a region of resistance only observed while the germanium atoms are on the move during switching. The negative resistance region during SET is used to account for the injection of holes that initiates the SET operation and a deeper understanding of its role is presently part of the work in progress. Switching lifetime or write/erase endurance of 100 million cycles was illustrated with operating voltages of 1V. Data retention in the reset state at 250C for 2,000 seconds was measured. However, the devices with dislocations in the super-lattice required a reduced temperature around 125C to display the same 2,000 seconds data retention performance.

TRAM future

The challenges for this device will be to obtain a better understanding of its operation and, in a practical sense, create in a production environment the multi-layer super-lattice memory cells in a memory array without defects. The IEDM paper does provide examples of structures with dislocations and further illustrates what might be described as forming process where about 100 of write/erase cycles were necessary to bring the device back to normal operating state. The mechanism involved to account for this effect was not presented.

As Ge vacancies are key to the most efficient operation of the TRAM, then controlling the vacancy level in a 1nm thick film will be an important fabrication parameter and represent a significant challenge.

When as is now claimed it is possible to have SET/RESET currents of equal value, 55uA, and with reset times of 5ns then the possibility of oscillations before the longer SET pulse ends needs to be further explored.

Good progress has been made, and the further development of these super-lattice memory devices looks to be worth further support to meet the many challenges.

-Ron Neale
??EE Times


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