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Optimise system energy consumption with MRAM

Posted: 29 Dec 2014 ?? ?Print Version ?Bookmark and Share

Keywords:Internet of Things? energy budget? MRAM? EEPROM? Flash?

For a number of wireless and portable applications, especially in the multiplying Internet of Things applications, there is a critical energy budget (total power consumed over time). As a member of the technical staff at Everspin Technologies I spend a lot of time working with system designers on applications for MRAM (magnetoresistive random-access memory). An idea that I have wanted to investigate for a long time is whether the fast-write and power-up-to-write times for MRAM can significantly reduce total system energy consumption compared to either EEPROM (electrically erasable programmable read-only memory) or Flash.

For this article, I compared system energy consumption in a typical data acquisition system using Flash, EEPROM, or MRAM. The comparisons showed that:
1. Non-volatile memory write time is a major contributor to overall system energy consumption, thus the shorter write time of MRAM can actually reduce total energy consumption.
2. Further system energy reductions can be achieved using a power-gating architecture with MRAM because its faster power-up-to-write time allows MRAM standby power to be reduced to zero.

Typical system
I used the schematic in figure 1 to represent the low-voltage dropout regulator (LDO), microcontroller (MCU), non-volatile memory, and a decoupling capacitor typical in data acquisition applications such as medical monitors, data loggers, etc. Other system components, such as sensors and the power they consume, were not considered.

Figure 1: Application with Flash or MRAM using power gating for standby mode.

The MCU was assumed to be in a low-power sleep state and with a periodic wakeup to make an acquisition of data. The data acquired was stored in the non-volatile memory, and then the system returned to the sleep state.

I compared non-volatile memory with a serial peripheral interface (SPI) and looked at only write operations, which typically consume much more power than read operations. The number of data bytes that can be written is four less than the number of bytes on the SPI bus, due to overhead of the write command, the WREN bit, and two address bytes. The number of bytes written to the non-volatile memory was selected as 4 and 46. Four is perhaps most likely, representing the storage of one data acquisition sample. Forty-six is the optimum amount of data that can be written to an MRAM when powered from a 1.0?F decoupling capacitor.

Power gating considerations
A few quick calculations revealed that the decoupling capacitor is very important when power gating. The energy used to charge the capacitor from zero is significant.

EEPROM can be powered directly from the I/O of a standard microcontroller, typically 4 mA, and consequently a small 0.1?F capacitor was used for decoupling. MRAM and Flash need more current than is available from a standard MCU I/O. For these memories I assumed a larger decoupling capacitor so that the Flash or MRAM could run on the energy stored in the larger capacitor.

Phases of the write operation
The energy consumption of the non-volatile memory was calculated during the phases of the write operation shown in figure 2.

Figure 2: MRAM VDD during power-up and access times using power gating.

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