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Modelling package parasitics within IBIS

Posted: 16 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:package parasitics? capacitance? inductance? IBIS? Input/Output Buffer Information Specification?

Lately, I've been getting many questions about package parasitics (capacitance and inductance) and how best to simulate these. How are they represented within an Input/Output Buffer Information Specification (IBIS) model? How relevant is package information at high frequencies? Can parasitic data can be used for both analogue and digital signals?

In summary, package parasitics can be modelled within an IBIS file using a number of methods that differ in their complexity and accuracy:

1. The simplest, but least accurate, method is to assume that all package pins are identical, uncoupled, and share common package parasitics, R_pkg, L_pkg, and C_pkg, defined under the [Package] keyword and illustrated below. C_comp is the input capacitance of the die (figure).

Figure: IBIS input model structure.

2. Unique parasitics, R_pin, L_pin, and C_pin, can be specified separately for each signal defined under the [Pin] keyword.

3. Advanced package models, which use RLC matrices that account for capacitive and inductive coupling between pins, defined under the [Package Model] keyword.

4. A combination of methods 2 and 3 for pins that aren't defined in the package model.

Electronic design Automation (EDA) tools let you specify the desired method of package modelling.

Some engineers who use mixed-signal IBIS models try to extract further value from IBIS and attempt to simulate analogue inputs/outputs to predict impedance match. It's important to understand that IBIS, unlike SPICE/Eldo, doesn't contain any functional information associated with analogue inputs/outputs. Moreover, many model providers simply don't, for example, measure these signals using a TDR (Time-domain reflectometer). It's only when simulations predict completely erroneous resultsand a lot of time has been wasteddoes the user question the suitability of the model.

Users of high-frequency, broadband, mixed-signal parts need to be aware that IBIS package parasitics are typically represented as a single-pole, lumped RLC, really only suitable for low-frequency analyses. Usually these will have been measured at a single, fixed frequency by the model provider. Some simulators convert the lumped L and C information to a distributed transmission line,

to approximate package parasitics.

For high-frequency, broadband devices, IBIS allows package effectstraces, bond wires, vias, plating bars, be represented as a distributed transmission lines using the Len parameter as shown below:

A1 Len=1.2 L=1.0n C=2.5p R=0.05

If the Len parameter is specified to be non-zero, then RLC represent distributed elements per unit length.

Have you used IBIS models for anything other than predicting digital SI, pin-to-pin crosstalk or simultaneous switching output noise? Have you tried converting lumped L and C package parasitics to approximate a distributed transmission line to predict the bulk-head match of a circuit containing a broadband ADC/DAC for example?

About the author
Rajan Bedi is currently CEO of Spacechips. Rajan worked at Astrium (now Airbus) for twelve years developing and researching space-grade electronics for telecommunication, navigation, Earth-observation and science missions. As Head of the Mixed-Signal Design Group, Rajan's team developed the hardware for the award-winning, channelising payload currently operating on-board the Alphasat telecommunication satellite.

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