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CEA-Leti describes true 3D monolithic integration

Posted: 09 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:CEA-Leti? TSV? 3D IC? monolithic integration? FDSOI?

CEA-Leti has released the test results on multi-layer transistors stacking for true 3D monolithic integration during a 3D-VLSI workshop preceding IEDM 2014, in San Francisco. According to the research institute, the technology is no longer dependent on tall through silicon vias (TSVs) and coarse redistribution layers typically used for wafer-on-wafer die stacking.

Only recently dubbed CoolCube for its future commercialisation, the technology can be essentially described as sequential 3D ICs manufacture, enabling circuit partitioning in 3D at all granularity levels, including at transistor or gate scale through a standard lithographic process.

The key difference with the "traditional" use of TSVs, where two or more processed dies are assembled one on top of another, is the transfer and molecular bonding of a thin Si wafer film, peeled off from a wafer blank after planarisation.

Because the transferred film is so thin and optically transparent, well under a micron (compared to around 50um for thinned wafers), the layer of transistors that are processed on top can be aligned to the bottom transistors with lithographic precision.

Hence the stacked layers can be connected at the transistor scale rather than just through the dies' metal pads.

Sequential 3D IC

Coarse grain to fine grain circuit partitioning for 3D circuits: (1) Memory/core on core, (2) Function unit block, (3) logic gate distributed across different layers, (4) transistor scale partitioning.

This approach was only possible through the use of a low-temperature-budget MOS transistor technology on top, the "COOL" layer processed under 600°C so as not to alter the first bottom MOS transistor layer.

This low-temperature fabrication allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.

3D monolithic integration

3D monolithic integration

In a paper titled "3D sequential integration opportunities and technology optimisation," Leti's Advanced CMOS laboratory manager Maud Vinet described the necessary 3D contact process between the two layers as being marginally higher than a standard tungsten contact plug in an oxide, with an additional height of the 3D contact in the range of 50nm.

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