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Processors from Cadence offer local memory power efficiency

Posted: 14 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? processor? local memory?

Cadence Design Systems Inc. has unveiled the 11th generation of the Tensilica Xtensa processors. According to the company, the Xtensa LX6 and Xtensa 11 processors enable users to develop innovative custom processor instruction sets with up to 25 per cent less processor logic power consumption and up to 75 per cent better local memory area and power efficiency.

The Xtensa 11 and Xtensa LX6 processors feature enhancements in flexible length instruction extensions (FLIX) for Xtensa LX6 that allow for very long instruction word (VLIW) instructions of any length from 4-16 bytes, resulting in code size savings of up to 25 per cent compared to prior Xtensa versions, thus enabling local memory and cache size reductions of up to 25 per cent for the same performance level. In addition, the devices feature an option for run-time power-down of portions of cache memories, yielding up to 75 per cent local memory power savings in select operating scenarios with dynamic cache-way control.

The processors boast more efficient data cache block prefetch that lowers system power and boosts system performance by speeding functions such as MemCpy by 6.5 times faster and reducing the total number of system bus read operations by up to 23 per cent. Also, the solution offers reduced dynamic switching power of the processor logic gates by up to 25 per cent.

The latest versions of the Cadence Xtensa customisable processors are available.





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