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Avago's 56Gbit/s PAM4 SerDes aims at routers, switches

Posted: 15 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? SoC? PAM4? SerDes?

Avago Technologies has introduced what it claims to be the first 56Gbit/s pulse-amplitude modulation (PAM) 4 serialiser/deserialiser (SerDes) designed for next-generation routers and switches.

OEM customers are presently designing advanced ASIC SoC systems in 28nm and 16FF+ process technologies utilising the Avago PAM4 SerDes cores.?

PAM4 technology enables future scaling of core/metro router and hyperscale data centres by more than doubling link throughput to 56Gbit/s from 25Gbit/s, in full duplex per differential pair. Rack-level applications will particularly benefit from PAM4 technology realising advantages in space, power, cost and simplified cabling.

The 56Gbit/s PAM4 SerDes is designed to support a range of copper and optical interconnects ranging from chip-to-chip, chip-to-module, low-cost direct-attached cable and copper backplane down to 35dB loss. The SerDes supports speeds from 1Gbit/s to 56Gbit/s, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel and OIF CEI NRZ speeds, providing investment protection and a forward-looking architecture path to networking, compute system vendors and mega data centre companies.??

By also targeting emerging OIF CEI-56G-VSR and IEEE 802.3bs (400GE) electrical standards defining next generation chip-to-module interconnect, the 56Gbit/s PAM4 SerDes provides the additional benefit of enabling the same PAM4 signalling deployment on front side and back side interfaces, thus increasing SoC use case flexibility and reusability across hardware platforms.??

The 56Gbit/s PAM4 SerDes, now available in silicon, is running PRBS31 traffic, error-free, across various interconnects, thus reducing ASIC development risk and accelerating Avago customer system deployment.

-Jean-Pierre Joosting
??EE Times Europe

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