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Memory VIP speeds up mobile design verification closure

Posted: 22 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? verification IP? SystemVerilog? mobile design? eMMC?

Synopsys Inc. has revealed its plan to extend its memory verification IP (VIP) portfolio to include key titles for the mobile industry. The company's memory VIP is based on a native SystemVerilog architecture to streamline ease of use, and allow integration and configurability. These advanced features will enable project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols to expedite verification closure of mobile block, subsystem and SoC designs, noted Synopsys.

VIP for the emerging UFS and UniPro protocols also includes self-contained compliance test suites to accelerate verification closure and eliminate the tasks of developing a verification environment and tests. The test suites are delivered as native SystemVerilog source code for improved reuse, extensibility and debug. The JEDEC eMMC VIP includes support for eMMC card and host. All verification IP and test suites are based on a consistent SystemVerilog UVM architecture to enable easy adoption.

Synopsys' portfolio of bus, interface and memory VIP includes built-in coverage and verification plans to enable coverage closure. It also includes support for Verdi protocol analyser to provide protocol-aware debug. Synopsys VIP for the JEDEC UFS, MIPI UniPro and JEDEC eMMC memory protocol specifications provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence, the company added.

Synopsys Verification IP for UFS, MIPI UniPro and eMMC are available standalone and as part of the Synopsys VIP Library as well as in the verification compiler product. The Synopsys DesignWare digital controllers for UFS, MIPI UniPro and eMMC are also available.





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