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Performing automatic ASIC-to-FPGA conversion

Posted: 28 Jan 2015 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC? FPGA? prototype? software development? debug?

As electronic companies design today's leading-edge ASICs, rising costs and shortening development schedules are requiring ASIC designers to develop an early prototype. Prototypes are used to help accelerate hardware and software schedules and complete system verification. Companies often fulfil their prototyping requirements with platforms based on FPGAs, which provide developers the opportunity to have a hardware platform early in the design cycle.

Using a prototyping platform for initial software development has become standard practice that allows for faster software development and debug. Development work can be compiled and debugged on real hardware allowing needed bug fixes to be integrated early in the development cycle. In addition, the verification teams can utilise the prototyping platform to accelerate verification by allowing the testing of designs on FPGA hardware platforms very early in the process, thereby gaining a significant advantage in advance of final silicon becoming available.

All of this leads to the fact that many ASIC teams are tasked with creating an FPGA-based prototype to enable hardware-based debug, test, and early software development. In most cases, the design team provides nightly or weekly builds of the most current prototype to the software development and verification teams. These ongoing changes to the ASIC design mean that the hardware designers require some method of generating corresponding updates to the prototyping platform.

FPGA synthesis tools like Synplify Premier help automate the conversion of the ASIC design into its FPGA equivalent by directly reading the ASIC design files, including DesignWare IP blocks, ASIC RTL, constraints, and Verilog files. In addition, the tools provide an easy path to implement "FPGA friendly" designs by utilising side files that specify which circuitry to remove, stub out, or substitute, and to automatically convert ASIC clock architectures into equivalent FPGA clocking structures.

Figure 1: Direct support of golden ASIC files and conversion side files.

By using the ASIC source files directly, designers can update and patch the main ASIC code without having to struggle with the conversion into a FPGA prototype. This helps eliminate duplicate code bases and synchronisation issues through the direct import of the "golden" set of ASIC source files, such as RTL (including Verilog, VHDL, and SystemVerilog).

One area of particular note is the inherent complex clocking circuitry that often includes a large number of gated and internally generated clocks in an ASIC design. The Synopsys FPGA synthesis tools provide designers with an ability to address these complex clocking schemes by providing a path for automated gated clock conversion. It is not always necessary to convert all clocks from an ASIC design, but fitting the design into the FPGA device and meeting timing objectives are the ultimate goals.

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