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How to prevent latchup in CMOS

Posted: 05 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? latchup? PN junctions? inverter? power supply?

Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions to which they were connected.

To understand why latchup can occur, consider the simple inverter in figure 1.

The inverter consists of two MOS transistors. Also placed somewhere nearby (not necessarily between the devices as in the diagram) are well and substrate taps to bias the well to VDD and the substrate to VSS. There are also parasitic bipolars: a vertical PNP device formed by the P+/N well/P Substrate junctions, and a horizontal NPN device formed by the lateral N+ / P substrate / N well junctions.

Figure 1: A typical CMOS inverter cross section, showing parasitic devices.

A simplified schematic of the parasitic elements is shown in figure 2. The shunting resistors Rwell and Rsub represent the effective resistance from the well tap to the PNP base and the substrate tap to the NPN base.

For the circuit to latch up, several conditions must be met1.
1. The transistor current gain product of Qn and Qp must be greater than 1 such that the structure will remain latched.
2. Both emitter-base junctions of Qn and Qp must be forward biased to initiate and sustain latchup.

The power supply must be able to sustain the supply current drawn while latched (the holding current) and the supply voltage (the holding voltage).

Figure 2: Simplified schematic of the parasitic devices in the previously shown CMOS inverter layout.

The holding current has been shown(2) to be strongly dependent on Rwell and Rsub. The physical reason is clear: a low Rwell or Rsub means a higher current has to flow to maintain forward bias on the base-emitter junctions. Note that figure 1 represents a 'strong' layout as the substrate and well taps are between the devices; if they were on the other sides of the devices then Rwell and Rsub would increase and the circuit would become more sensitive.

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