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Flash FPGAs offer designers enhanced flexibility

Posted: 04 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:flash? FPGA? SRAM? AES256? SHA256?

These days, flash-based gate arrays are more than just a collection of configurable gates. The arrays now contain many other dedicated functions that reduce system design time, improve logic utilisation, lower system cost and power, and deliver better performance than equivalent functions implemented in just the configurable logic. Predesigned function blocks conserve the basic logic resources of the FPGAs and, in some cases, implement functions not possible to build using the logic fabric in the FPGA.

Why flash?
In many applications SRAM-based FPGAs can offer similar features and functions. However, since the FPGAs use SRAM cells to hold the configuration patterns, when power disappears so does the configuration pattern. When power is restored, the system must reload the configuration pattern, typically through a serial interface, and that can take tens to hundreds of milliseconds.

In contrast, in flash-based FPGAs non-volatile memory cells hold the configuration pattern right on the chip, and even if power is removed the contents of the flash cells stay intact. Thus when the system restarts, the FPGAs power up in microseconds, saving time and allowing the system to recover quickly from a power failure or a restart.

In the past, flash-based FPGAs trailed behind the SRAM-based devices in density, performance, and on-chip features such as processor cores, high-speed I/O channels, and other functions requiring high density. This trailing edge was mainly due to the challenge of shrinking the flash memory cell, which typically required larger dimensions than the rest of the logic on the chip. The larger dimensions, in turn, resulted in slower performance and the inability to integrate high-performance processor cores and other functions on the FPGA.

However, advances in process technology now allow the FPGA designers to shrink the flash configuration cells and integrate them into advanced logic processes, enabling high-performance flash-based FPGAs to deliver features and functions comparable to or even better than what SRAM-based FPGAs can deliver, and often at a lower system cost. Additionally, since an external configuration memory is not needed, the flash-based arrays have a reduced system footprint and consume less power.

Flash technology has transitioned from a speciality process to the mainstream, allowing flash-based FPGAs to compete in cost-sensitive markets while delivering logic densities of over 150k logic (figure 1). The integrated functionality of flash FPGAs also delivers system-level solutions which help reduce system complexity, lower system power and reduce overall system cost.

Figure 1: For FPGAs with up to 150k logic elements, there are many available market opportunities that range from about $300 Million for the Defense and Security markets to $500 Million for the combined wireline and wireless markets.

Figure 2 provides a short comparison of the features integrated into flash-based FPGAs vs comparable density SRAM-based FPGAs.

Figure 2: Feature set comparison of flash vs SRAM-based FPGAs (for devices with sub-150k logic elements).

While there is much in common between flash-based FPGAs and comparable density SRAM-based FPGAs, there are also many significant feature differences aside from the flash or SRAM configurability. Chief among these differences are the quantity of I/O pins, the number of SERDES channels, and the inclusion of a high-performance memory sub-system as well as embedded security functions including AES256 or SHA256 encryption/decryption capabilities.

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