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ARM, Synopsys join forces for next-gen mobile device designs

Posted: 05 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:ARM? Synopsys? processor? compiler? mobile device?

Synopsys Inc. has partnered with ARM to leverage the IC Compiler II place and route solution at enabling superior implementation of high-frequency, power-efficient designs by delivering a Reference Implementation flow for the ARM Cortex-A72 processor. According to the companies, the combination of RTL synthesis and place-and-route solutions with a Reference Implementation flow optimised for the CPU allows engineers to develop advanced designs for next-generation mobile devices.

Based on the results of previous collaborations, including Reference Implementations for ARM Cortex-A57 and Cortex-A53 processors, the Reference Implementation for the Cortex-A72 core takes advantage of ARM POP IP in 16nm FinFET Plus process, Synopsys HPC methodology and the latest tools and features in the Galaxy Design Platform. To achieve up to 2.5GHz performance in a mobile computing power envelope, the Reference Implementation includes support for Synopsys' Design Compiler Graphical tool for RTL synthesis, IC Compiler and IC Compiler II for place and route, and PrimeTime solution for signoff and physical ECO.

IP suite promises premium mobile experience
The premium mobile experience IP suite addresses the ever-increasing demands of end-users for their primary, always-connected mobile devices capable of creating, enhancing and consuming any content.

In addition, the Reference Implementation is compatible with the Lynx Design System. Synopsys technology key to achieving this performance and power level includes: physical guidance for a predictable implementation flow, concurrent clock and data optimisation for a boost in frequency, advanced clock gating, low-power clock tree synthesis and multi-bit register optimisation for dynamic power savings, and signoff leakage recovery for further power reduction.

IC Compiler II is Synopsys' latest offering in place-and-route and is a full-featured, production-ready netlist-to-GDSII implementation system delivering the highest throughput and productivity along with the best quality of results, stated the companies.

Early adopters of ARM's suite of IP for a premium mobile experience, which includes the ARM Cortex-A72 processor, CoreLink CCI-500 interconnect, Mali-T880 GPU, Mali-V550 video processor and Mali-DP500 display processor, have been successfully using Synopsys tools and methodology to design and verify their initial designs, the companies said. Building on previous collaborations to enable ARMv8-A based processor and advanced Mali GPU designs as well as the Reference Implementation for the Cortex-A72 core, Synopsys and ARM are collaborating to extend these solutions across the IP suite to include: optimised implementation with the Galaxy design platform including IC Compiler II; virtual prototyping with virtualiser development kits (VDKs) for ARM v8-A based cores; optimised simulation, formal verification, advanced debug, verification methodology, as well as the next-generation verification IP, verification compiler product and ZeBu solution for emulation; HAPS FPGA-based prototyping systems; and a full chip design environment with the Lynx Design System.

In addition, Synopsys Core Optimisation Services flaunt extensive experience helping designers optimise their CPU and GPU cores for performance, power and area.





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