Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Memory/Storage
?
?
Memory/Storage??

Tuning DDR4 signal paths with modern design tools

Posted: 10 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:RAM? DDR4? DDR3? dual-inline memory module? PCB?

The latest standard in the race for ever-denser and ever-faster dynamic RAM is DDR4, short for double data rate, fourth-generation synchronous dynamic random-access memory. DDR4 memory will operate at speeds between 1600 MHz and 3200 MHz, compared to speeds between 800 MHz and 2400 MHz for DDR3 memory. Standard memory modules will be denser, too. The DDR4 standard specifies DIMMs up 128 Gbytes, compared to a maximum of 16 Gbytes for a DDR3 DIMM.

DDR4 modules employ a hybrid topology. DDR4 designs have parallel, length-matched transmission lines for the data bus and daisy-chained, length-matched transmission lines for the clock, address, and control bus lines. The latter type of topology is sometimes called "fly-by" topology. Each signal is routed sequentially from one device to the next and is then terminated after the last device.

This topology eliminates reflections, but the downside is that the signal delay increases for each successive device in the chain. However, this topology can be used when the output device can compensate for this signal skew, using a technique known as "signal leveling."

Figure 1 shows how an address or control line would be routed to each of the SDRAM devices on a DDR4 dual-inline memory module (DIMM). The lengths of the bus connections from connector to first device, and from device to device, must be tuned so that commands arrive at each chip center-aligned to the clock. The DDR4 specification spells out the timing requirements for each of the segments of this address or command line. Each segment must be treated as a transmission line, which is why the segments are designated as TL0, TL1, etc.

Figure 1: DDR4 DIMMs use a "fly-by" topology for address and control lines.

To ensure that the DDR4 module will work properly, you would first tune the length of the signal path from the DIMM connector to the first SDRAM device. This path includes TL0, TL1, and TL2. Once that path has been tuned, you then go right down the daisy chain, tuning the paths between devices. The signal path from the last device in the chain to the termination, which includes TL5, does not need to be matched to the other sections, but its length should be limited so that the line is properly terminated.

1???2?Next Page?Last Page



Article Comments - Tuning DDR4 signal paths with modern...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top