Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Verilog-AMS vs SPICE view for power management

Posted: 12 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:analogue mixed-mode simulations? AMS? Verilog? IP? SoC?

The SoCs produced nowadays offer a high level of functionality, driving a wide range of applications, while becoming more and more cost effective. This means that the complexity of the SoC too is reaching an all-time high. Dozens of analogue IPs and digital IPs are integrated into the same SoC. It also contains multiple voltage domains that often simultaneously support a combination of Internal and External regulation modes. The importance of a high level of power efficiency also means that several modes like standby, low power, reduced clock mode, etc. also need to be supported.

To achieve first pass success of such complex SoCs in silicon, a robust pre-silicon verification methodology needs to be implemented. The high level of analogue IPs in these SoCs necessitates the need for analogue mixed-mode simulations (AMS) that target the various features and modes being supported. In addition many of these simulations also need to be run across process and temperature corners. This results in an AMS simulation count that runs into the 100s. Defining, implementing these simulations accurately is a complex task. Moreover simulating all of them is quite computationally intensive.

Thus it is important to weigh the pros and cons of using a Verilog/Verilog-AMS view with respect to a SPICE view for all the analogue IPs within a SoC. This process needs to be carefully repeated for different AMS simulations, each targeting a different type of check. Verilog/Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. In this paper we comparatively analyse the usage of both the views from a power management perspective.

Voltage regulator start-up
Every System-on-Chip requires a DC power supply to operate. Usually, supplies of several different levels, e.g. 1.2V, 3.3V, etc. is required for the same chip. The 3.3V HV supply is used for all the analogue functionality, while the 1.2V LV supply is used for the core or logic side operations. In such cases at-least one of the required supplies is generated using a regulator on or off the chip, e.g. using an on-chip voltage regulator to generate 1.2V LV supply from 3.3V HV input. A voltage regulator can thus be said to perform an operation of maintaining an almost constant output voltage even against some variations of the input voltage and/or load on the regulator, provided these variations are within design specification for the said voltage regulator.

The voltage regulator is part of a bigger system called a Power Management Controller or PMC. A PMC contains other blocks essential for the correct operation of the voltage regulator like bandgap reference generator (BGR), power-on resets (PORs), low voltage detects (LVDs), high voltage detects (HVDs), test mode support, etc.

Figure 1: Power management controller.

The BGR provides a highly stable reference voltage to every other circuit on the SoC. It uses some circuits that drift proportional to temperature (PTAT) and some that drift complementary to temperature (CTAT); with the net result being that they both cancel each other out, hence making the BGR highly resilient against change of operation temperatures. The output of the BGR is given to a resistor ladder, from where various tap points provide several divided versions of the original reference. These divided versions can now be used as a reference for a variety of comparator based circuits.

PORs, LVDs and HVDs indicators are few such comparator based circuits. They can be placed on various supplies to track the level of that supply with respect to pre-defined thresholds. The POR indicates the time when the supply has reached above a level, roughly corresponding to the Vt (threshold voltage) of the devices. Before the POR is lifted the chip is said to be in an unknown or garbage state. Arrival of the POR takes the chip to a known reset state.

1???2???3?Next Page?Last Page

Article Comments - Verilog-AMS vs SPICE view for power ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top