Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Researchers envision thermoelectric nanowires in chips

Posted: 11 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Thermoelectric nanowires? chips manufacturing?

When Moore's Law was formulated, no one guessed that the chips would start melting down when their speeds approached 5GHz, so instead of building faster and faster chips they started making multi-core chipsa Band-Aid solution at best.

But now for the first time researchers at Sandia National Labs have found a room-temperature electroforming technique to remove heat at its source. The process controls crystal orientation and crystal size using antimony salts and Bismuth-antimony (Bi-Sb) alloys. The uniformity of the single process holds open the promise of continued speed-scaling for future complementary metal oxide semiconductor (CMOS) chips. The nanowires are about 70-75nm in diameter and several microns long, starting from a poly nano-crystalline structure to near single crystals of 2 to 5?m. The work was led by Graham Yelton, a Sandia material's specialist.

Yelton said he can envision several methods of embedding his thermoelectric nanowires into chips during manufacturing. "One pathway is from the back side," Yelton told EE Times.

There are many other uses for Yelton's and his Sandia colleague's thermoelectric nanowiresuch as wrapping exhaust pipes on automobilesbut cooling semiconductor chips is one dear to their heart and for which there was Department of Energy funding available.

Thermoelectric nanowires

Graham Yelton and Sandia National Laboratories colleagues developing a single electroforming technique that enhances thermoelectric performance: crystal orientation, crystal size and alloy uniformity. (Photo by Randy Montoya) (Source: Sandia National Labs)

Besides pulling heat from a chip's backside, which is relatively easy since usually no circuitry is there, Yelton has also set as a goal to draw energy from top-side connections where most of the heat is generated in the first place.

"Low electrical resistance and the top-side contacts are the next engineering hurdles to overcome to commercialise our thermoelectric nanowires," Yelton told us.

The trickiest part of threading thermoelectric wires on the topside of chips will be developing an excellent thermal contact that does not interfere with electrical functions. Unfortunately, this research will be expensive and involve a lot of supercomputer time as well as trial-and-error experiments to discover the right mix of materials and mounting techniques.

"We need funding to carry on this work. The next step is to develop top-side contacts. After that, the next milestone would be to engineer mounting the arrays in the key areas of interest," Yelton told us.

Despite the progress made, Yelton claims thermoelectric materials are in their infancy and will be improved tremendously as their properties become better understood. Some of the knowledge that needs to be gained include uniform composition of millions of nanowires side-by-side, uniform crystal size to improve efficiency and more precise orientation for improved energy flow.

- R. Colin Johnson
??EE Times U.S.

Article Comments - Researchers envision thermoelectric ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top