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LDO design techniques in the era of miniaturisation

Posted: 26 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Power management? voltage regulator? LDO? NMOS pass transistor? amplifier?

Power management is one of the key challenges to the ultra-miniaturisation of electronic systems. As any electronics engineer knows, when overall system sizes shrink the amount of area available for energy storage and energy conversion shrinks with it. This is happening in many market-growing applications, such as implantable medical devices, Internet-of-things (IoT) electronics, and wearable electronics. While the size of the electronics continues to scale, the batteries and capacitors required to store energy are not keeping up. The consequence is that often times the area required for energy storage and power management dominates the overall form factor of the final product.

Due to these area limitations energy must be stored in an efficient form. Often times the most efficient form is at a higher potential and with significant noise components. A voltage regulator C such as an LDO C is then required to regulate this supply voltage down to the level at which the system operates.

A key figure of merit in low power LDO design is current efficiency. Current efficiency is defined as the ratio of Iload to Itotal. This ratio is the percentage of overall power drawn from the power supply that is delivered to the load. For high power applications it is common for this number to exceed 99 per cent. However, this is very different in low power design. If, for example, the total load current is 10uA, every 1uA of quiescent current in the LDO results in a 10% drop in current efficiency. In an already power constrained system this loss in efficiency can be catastrophic. As such, design methods that minimise the overall LDO quiescent current are critical. A properly designed LDO will maintain overall system efficiency and long battery life, minimising the need for large energy storage elements.

A short LDO design overview
The figure shows an LDO block diagram utilising an NMOS pass transistor. Consider applications where the unregulated power supply voltage (Vsply) is much greater than the regulated output voltage (Vreg). Here, a simple NMOS pass transistor architecture is usually the best choice.

Figure: LDO block diagram with NMOS pass transistor.

This architecture has many desirable properties, two of which are trivial frequency compensation and a small FET area. A small FET area is a result of the higher mobility of charge carriers in NMOS FETs (electrons) versus that of PMOS FETs (holes). The ease of frequency compensation is due to the dominant pole being at the gate of the NMOS pass transistor instead of at the output node.

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