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Keysight sol'n tests DDR4 x16 designs with logic analyser

Posted: 20 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:logic analyser? DDR4? x16? BGA interposer? W4631A?

Keysight Technologies introduced a connection hardware that resolves probing connectivity issues. The ball grid array (BGA) interposer solution is targeted at testing DDR4 x16 DRAM designs with a logic analyser.

The interposer provides fast, accurate capture of address, command and data signals for debugging designs and making validation measurements. The W4631A BGA interposer, the fastest interposer solution available for use with a logic analyser, is used with Keysight's E5849A probes for high-data-rate DDR4 DRAM designs.

The W4631A interposer solves probing connectivity by providing access to DDR4 x16 DRAM signals critical to debug and validation efforts. The probe works in many existing designs and eliminates the need for up-front planning or redesign.

W4631A

The probe connects directly to the balls of the DRAM with a DDR4 96 ball riser (included) or an optional third party socket (not provided), enabling operation and acquisition of high-speed DDR4 signals with low loading and minimal impact to signal integrity on embedded system design. The interposer solution is designed to be used with the U4154B logic analyser system. The Keysight W4631A BGA interposer is designed for data rates up to 3.2Gbit/s.

Key features:

- The B4622B DDR2/3/4 and LPDDR/2/3 protocol compliance and analysis toolsetproviding four different software tools: two for functional protocol compliance checks, one automated physical address trigger setup tool, and one tool that provides an overview of system performance through bus statistic information and a histogram view of address access. These tools help reduce memory designers' troubleshooting time and increase productivity and efficiency in DDR design validation work.

- The B4621B DDR2/3/4 protocol decoder softwarefor translating acquired signals into easily-understood bus transactions showing associated data bursts. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command. The B4621B bus decode software anticipates key system attribute inputs from default DDR2, DDR3 or DDR4 probing configurations or the DDR setup assistant tool to accelerate decode of DDR2, DDR3 or DDR4 bus signals.

- The DDR eye scan/eye finderproviding eye-scan capability to automatically place the sampling point in both time and voltage within the eye on each individual channel for optimal sampling reliability. The DDR eye-scan display provides bus-level signal integrity insight for a qualitative comparison of all signals scanned under the same conditions.

- The DDR setup assistant toolfor guiding users through a short series of questions and pull-down menus to assist in tuning state mode measurements on DDR2/3/4/ or LPDDR2/3/4 measurements.


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