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Marvell unveils novel interconnects, memory architectures

Posted: 25 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Marvell? interconnect? memory? DRAM? ISSCC?

Mixed reactions for MoChi, FLC

Both initiatives were pet projects worked in weekends over the past several years by the CEO who started his career as an analogue circuit engineer. A team of more than 100 Marvell employees now have the technologies running in simulation.

Initial reactions were mixed with many expressing support for the boldness of the initiatives but scepticism about their potential for success. The industry has seen many system-in-package concepts and experiments in new memory hierarchies, they noted.


Marvell sees MoChi links used to connect mobile app processors with radios and other peripherals.

"I'm not sure MoChi is anything beyond what we see today," said Mike Demler, senior analyst with the Linley Group.

He noted Sutardja slides showed future smartphone processors using MoChi links to connect to separate radio and peripheral chips (above), just as they do today with PCI express. Demler also noted potential reliability issues if SSDs are used for primary storage, given their relatively limited read/write cycles.

The FLC approach will require support from operating systems to reach its full potential, but it will deliver gains even with existing code, Sutardja said. The idea a kind of virtual main memory came to the Marvell CEO while staring at a class manager screen on a PC, he said.

"Most processes were idle, zero per cent, in aggregate these idle processes take a lot of expensive DRAM. I thought maybe it's possible to cache only active processes in less DRAM and leave inactive ones in cheaper memory."

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