Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Marvell unveils novel interconnects, memory architectures

Posted: 25 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Marvell? interconnect? memory? DRAM? ISSCC?

MoChi and FLC used in tandem in future 2.5D chip stacks

MoChi and FLC could be used in tandem in future 2.5D chip stacks, Sutardja said.

Low miss rates and thin laptops

FLC delivers decent cache miss rates

FLC delivers decent cache miss rates, according to Marvell's initial tests.

The MoChi interconnects could enable the long held vision of $100 laptops for developing markets, Sutardja added.

MoChi applications

- Rick Merritt
??EE Times


?First Page?Previous Page 1???2???3



Article Comments - Marvell unveils novel interconnects,...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top