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Intel's 14nm process churns out world's smallest SRAM

Posted: 25 Feb 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? SRAM? DRAM? ISSCC? 14nm?

Intel is set to unveil what it boasts are some of the world's smallest DRAM and I/O circuits during this year's International Solid-State Circuits Conference (ISSCC) as a form of validation of its 14nm process technology. The company will describe a 0.0500 ?mm2 SRAM bitcell capable of storing 14.5Mb per mm2. At 0.6V, the 14nm cell still runs at rates up to 1.5GHz.

The cell is part of a memory array will be widely used in Intel's future SoCs such as cellular modems that use hundreds of Mbits on a die, said Kevin Zhang, an Intel fellow. In another paper, Intel will describe a 14nm serdes transmitter that can signal rates up to 40Gb/s using either NRZ or PAM-4 modulation. At 0.03mm2, Intel claims it is the world's smallest transmitter delivering more than 25Gb/s.

Intel's 40G transmitter

Intel's 40G transmitter embraces two modulation schemes to keep eyes open.

Another paper will report on a 10Gb/s serial link for PCI Express made in the 14nm process. It consumes just 59mW and takes up 0.065mm2 of silicon area.

Wafers are more complex and expensive in the 14nm process which requires double patterning and thus more masks. However, greater gains in density means overall cost per transistor continued to decline at 14nm, something Intel expects to continue for the next two nodes, said Mark Bohr, an Intel senior fellow, echoing comments made in September.

"Moore's Law can continue beyond 10nm with new materials and device structures and by close collaboration of process and product designers," Bohr said. "I still believe 7nm without extreme ultraviolet lithography can deliver improved cost per transistor, but exactly how I'm not ready to disclose," he said.

Intel's view flies in the face of the rest of the industry that is saying the FinFET processes at 14nm to 16nm come at higher costs.

Stepping up the pace at 10nm

Intel admits production yields of its 14nm node were delayed due to the increased complexity of more mask steps due to double patterning. But Bohr expressed confidence that should not happen again at 10nm despite the need for triple patterning and even more masks.

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