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HyperRAM from Spansion touts up to 333MB/s read throughput

Posted: 04 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Spansion? HyperBus? RAM? MCU? SoC?

Spansion has rolled out its HyperRAM memory, a companion to its previously announced HyperFlash memory. The latest offering will claims to provide a simple and cost-effective solution for SoCs and MCUs, where both the flash and RAM are connected on the same 12-pin HyperBus interface. Featuring a read throughput up to 333MB/s, the HyperBus devices allows fast boot, graphics display and real-time XIP applications, indicated the company.

HyperRAM memory promise to offer a scalable solution for extending fast read and write operations externally, allowing fast delivery of high-resolution graphics in the early part of the boot process for automotive, industrial and IoT applications. It also cuts the number of pins that would normally be required to support standard DRAM, resulting in reduced PCB complexity and cost.


Spansion HyperRAM memory can operate at frequencies as fast as 166MHz in DDR mode with a fast, random initial access time of 36ns. Faster read access means less compressed, higher resolution graphics can be read, resulting in a sharper display, noted the company.

Spansion sees HyperRAM as an alternative to the commonly used options of SRAM or PSRAM using a parallel bus with more pins, he said. The company was able to leverage more than four years of development on its HyperBus and HyperFlash technologies and apply it to the development of HyperRAM, stated the company. Architectural changes were made, with addressing and data running in parallel to facilitate faster communication with the RAM. The challenge in the design process was to avoid conflicts.

Spansion's HyperRAM

Like its HyperFlash does, Spansion's HyperRAM connects to the company's proprietary 12-pin HyperBus Interface.

Spansion's 64Mb HyperRAM will be sampling in 2Q15. It will be available in both 3V and 1.8V versions packaged in the market compatible 5x5 array BGA.

The Spansion HyperFlash memory family will offer 3V and 1.8V power-supply versions and initially include three densities: 128Mb, 256Mb and 512Mb, with 512Mb samples available.

HyperFlash memories will be available in a space-saving 8mm x 6mm ball grid array (BGA) package. Spansion HyperFlash memory devices provide a migration path from one Quad SPI to two Quad SPI to HyperFlash memory, allowing system applications to be scaled to different levels of flash performance when paired with compatible controllers, giving OEMs the ability to offer different product models with a single design.

The 12-pin Spansion HyperBus interface consists of an 8-pin address/data bus, a differential clock (two signals), one chip select and a read data strobe for the controller, reducing the overall cost of the system.

Processors that have been publically announced to support the HyperBus interface include the Freescale MAC57D5xx automotive DIS MCU, the Spansion FM4 S6E2DH general purpose MCU and the Spansion Traveo S6J324C and S6J326C automotive MCUs.

- Julien Happich
??EE Times Europe

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