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Addressing difficult thermal analysis problems

Posted: 10 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:application specific integrated circuits? ASICs? ASSPs? Thermal test chips? TTC?

Both contain the same number of cells and, therefore can dissipate the same amount of power and both offer a centre diode for temperature sensing. For uniform heating, both operate the same and the only difference would be the voltage and current needed to generate the same amount of power dissipation. For example, see figure 4. The 3X5 array has 5 series strings of resistors with each string having a resistance of about 37.5? (= 5 X 7.5?). Paralleling these strings results in a total resistance of about 6.25?. For 10W of power dissipation, a voltage of 7.9V @ 1.265A would be required.

Figure 4: A 3 x 5 TTC array.

The 5X3 array, shown in figure 5, has 10 series strings of 3 resistors with each string having a resistance of about 22.5? (= 3 X 7.5?). Paralleling these strings results in a total resistance of about 2.25?. For 10W of power dissipation, a voltage of 4.74V @ 2.1A would be required.

Figure 5: A 5 x 3 TTC array.

Either approach works but the preference is to go with the lower current alternative since it is less stressful and will require smaller trace widths on the board where the packaged chip is mounted.

Distributed heating is actually more representative of what one might expect to see in a large ASIC or ASSP. Certain parts of the circuit that are designed for higher speed or must manage greater power are expected to dissipate more heat. Chip designers will want to know how hot these hot spots actually get and how the heat might affect circuitry on another area of the chip that might have some sensitivity to heat, such as a precision voltage reference.

TTCs are designed to accommodate either wire-bond or bumped wafer flip chip packaging. In the wire-bond configuration, the pads surrounding each TTC are connected to their adjacent neighbour with metal. Only when the die is sawn into its desired configuration (2x2, 5x5, 7x9, etc.) is the connection severed. Conventional wire bonding techniques pretty much limit package pinout access to only those pads around the periphery of the array. Due to the way the masking is done on the wafers, the maximum chip size of wire bond chip version, is a 40X40 array, (1,600 TTCs occupying a total of 10,000mm2 ~100mm X ~100mm).

When an application calls for a more localized heating, for power mapping purposes, the flip chip design is ideal. With no internal interconnects between the TTC in the array, all bonding pads are accessible. For example, for an 8 x 8 TTC array, heat can be generated at selected cells (figure 6).

Figure 6: Individual cells can be powered to simulate high power dissipation portions of the IC. Temperature sensing diodes in these and all other cells can then be used to measure heat transfer across the die.

Unit Cell specifications for each TTC are important to understanding the overall expected performance of the array being used to simulate the new IC under development (figure 7).

Figure 7: Specifications.

In addition to single chip packages, TTCs can also be obtained in custom stacked die configurations (figure 8) as well as multi-chip (horizontal layout) packages and package on package components. Custom packaging services are also available for those requirements that cannot be addressed by the standard packages described above.

Figure 8: Wire bond 1 X 1 chip mounted on a wire bond 2 X 2 chip.


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