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Addressing difficult thermal analysis problems

Posted: 10 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:application specific integrated circuits? ASICs? ASSPs? Thermal test chips? TTC?

TEA recently introduced a new TTC Unit Cell size version that is 1mm X 1mm and contains a single heating resistor and a single temperature sensing diode. The smaller Unit Cell allows for greater power mapping capability. Both TTC Unit Cell sizes are available in 150mm (6") diameter wafer form as well as sawn array chips.

Using re-distribution metal
An Re-Distribution Layer (RDL) is used to redistribute the electrical contact pads 每 either wire bond or bump 每 into a configuration other than that originally designed on the chip. Some reasons for this are:
???Mounting a chip onto BGA package substrate originally designed for a different chip pad configuration;
???Wire bond chips may have a single row of wire bond pads in the centre of the chip.
???Stacked chips may require all wire bond pads along one chip edge.

The process for creating an RDL on the wafer consists of creating one or more metal layers between insulation layers. The metal layers are etched to form traces that connect the existing chip contact pads to created new pads in desired locations.

Depending on the trace routing complexity, there will be multiple layers of metal and insulator stacked upon one another. The new pads can be used for wire bonding connection or act as the base for adding Flip Chip bumps.

Figure 9 is a TTC-1002 2X3 array with an RDL that provides for wire bonding either along specific locations on the periphery or down the centre of the chip. The RDL is a custom requirement that needs to be discussed in detail with TEA before any implementation can begin.

Figure 9: Re-distribution Layer to align bonding pads.

How hot is hot?
Calculating power density using empirical data derived from thermal test chips, IC designers and packaging engineers can model the actual performance of a product well in advance of committing a design to silicon or a package to hard tooling.

Semiconductor process advancements are merging heretofore incompatible pieces of complex systems onto a single substrate. Gone are the days of isolating the power elements to their own heat sunk packages. Now they reside a few microns away from temperature sensitive structures. Something has to give. Or does it?

The use of thermal test chips allows designers to precisely pinpoint the heat sources on their designs and simulate its effect on the performance of the entire system. Take the 2.54mm x 2.54mm Unit Cell discussed earlier. With its two 7.6次 resistor heating elements, each capable of handling 1 Amp at 6V, the cell can dissipate 12 Watts of power. Its area (6.45mm2) yields a power density of 186W/cm2. The newly introduced 1mm x 1mm Unit Cell with its single 10.5次 resistor heating element, capable of handling up to 0.55 Amps at 5.5Volts, can dissipate 3 Watts of power. Its area (1mm2) yields a power density of 300W/cm2.

Combining Unit Cells into an array derates these figures slightly due to the additional silicon required for saw streets between the cells. For example a 10 x 10 array of the 6.54 square mm cell has a power density of 182W/cm2, while a 10 x 10 array of the 1 square mm cell has a power density of 261W/cm2. These are exceptionally high PDs and are difficult to achieve by other means.

In power mapping applications, these high PDs per unit area offer the user an opportunity to better simulate power density levels resulting from multi-point localized heating in high performance CPUs and ASIC chips. Additionally, they can better simulate high power and high frequency transistors〞SiC (Silicon Carbide) and GaN (Gallium Nitride).

Although seldom discussed in public journals, the use of these analogue ASIC thermal test chips play an important role in allowing semiconductor manufacturers and companies designing their own ASIC/ASSP devices to get ahead of the curve by thermally engineering their silicon before going to production.

About the author
Bob Frostholm is Director of Marketing & Sales at analogue ASIC company, JVD Inc. Bob has held Sales, Marketing and CEO roles at established and start-up analogue semiconductor companies for more than 40 years. Bob began his career as one of the original marketers behind the ubiquitous 555 timer chip.

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