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Assessing the future of custom ASICs

Posted: 13 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:fables? ASICs? Moore's Law? Arduino? mixed-signal IP?

For decades, electronics product innovation has been incremental in nature, depending mainly on the next generation of semiconductors to deliver performance improvement. For almost 50 years Moore's Law has delivered 2x performance (power or cost) improvement in semiconductors every 18 months, outpacing any product or system level innovation cycle that could be achieved by even the most ambitious hardware teams. What has evolved is a "sit & wait" approach, to product innovation. However it is now clear that Moore's law is broken, and the implications are profound for hardware designers.

The semiconductor industry is consolidating, into fewer huge players. The fabless model is under increasing strain favouring only the most massively distributed companies. Hardware product teams can no longer sit-and-wait for performance improvement to be delivered by semiconductor companies, architecture is becoming more relevant, it becomes feasible C even necessary, for product teams to develop their own custom ASICs.

Here, I highlight some of the trends that have caused the hardware industry to favour a "sit & wait" approach to innovation, and looking forward 5 to 10 years, suggest what will be a fundamental shift in how hardware product innovation happens.

Hardware's innovation problem
Moore's Law has been relentless for almost 50 years.

A new hardware product has to be conceived, designed, prototyped, validated, mass manufactured, and distributed to enable traction and ultimately wide scale adoption by end users. A typical product innovation cycle can take two to three years to complete.

In the past, Moore's law will have delivered two cycles of process node shrinks in that same time frame, each of which delivering a 2x improvement, in performance, power, cost. This makes it impossible for hardware designers to outpace Moore's law using any other innovation approach. What has emerged as a result, is a "sit and wait" approach to innovation from product companies.

For semiconductor companies in turn to be competitive in the Moore era, increasingly required massive distribution and infrastructure to deploy millions of units per month. This favoured businesses only on the largest scale, and led to the adoption and evolution of the current fabless semiconductor model.

As the complexity of each new process node grew however, to maintain the pace of Moore's law, fabless semi companies needed to have two or three generations in development simultaneously, compounding the requirement of massive scale, and ultimately driving the consolidation we have been seeing since the beginning of the current decade.

Moore's law struggling to maintain an 18 month pace
Moore's Law is slowing down.

Arguably clock scaling as a performance metric, ended in 2003, since then multi-core architectures have been employed to achieve the performance gains predicated on Moore's Law, as shown in the figure.

Figure: The end of clock frequency scaling prompted the genesis of multi-core architecture.

Certain fundamental parameters have already hit a wall, such as Vth, Vddmin, Gate Oxide thickness.

This is not to say that scaling will not happen, it certainly will at least to possibly 5nm, somewhere between 2020 and 2030 (H. Lwai Microelecton. Eng 2009 , doi:10.1016/j.mee.2009.03.129), and there will still be some applications with unit volume sales that support the economics required.

However, we are not getting 2x improvements every 18th months, and this has profound implications for hardware innovation, as the "sit & wait" approach to hardware and product innovation falls apart.

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