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Assessing the future of custom ASICs

Posted: 13 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:fables? ASICs? Moore's Law? Arduino? mixed-signal IP?

The key insight is, when you look at a typical two-to-three year product development timeline, in the post Moore era, there is ample time to execute this cycle in between process node releases. As a result there is now a compelling reason and time, to consider new innovative system architectures or build custom ASICs optimised for a specific product, since doing so beats the improvement that can be gained from process scaling alone.

Post Moore
In the post Moore's law world, architecture matters, optimisation matters, and a custom ASIC approach is beginning to re-emerge, as not just feasible, but a necessary option for many System Companies and OEMs.

In other words, there is a genuine market window for monetizing innovative product and hardware solutions, based on custom ASICs, instead of sit & wait.

Deceleration of Moore's Law is already showing its impact on markets that are not as sensitive to performance. Consider the rise of the Arduino platform. The Arduino took several years to gain popularity, with virtually the same hardware at its core since 2005.

Closer to home, consider the Iridium Satellite transceiver platform, S3 Group have developed 3 generations of custom RF & mixed signal ASIC solutions, in the same period as two process node developments, enabling Iridium and more importantly their customers benefit in terms of cost & form factor through innovative new architecture approaches, rather than process shrinks of the original ASSPs.

In what are now mature process nodes, ASIC development times are shortened considerably due to the availability of semiconductor IP, production proven on those nodes. As the process node shrink cycle lengthens, typical Product Development cycle now outperforms the process node cycle in delivering price/performance improvements.

Hardware optimisation becomes relevant
In the past there was little motivation to optimise hardware or architecture, when gains could be made by cramming more features into software, waiting for a semiconductor upgrade cycle and then it would start to run well as Moore's Law delivered semiconductor performance. Remember how slow WinXP and Vista ran when they first came out?

Megatrends like open compute projects, the maker movement, hardware hackathons, are all examples of (or reactions to) the realisation that gains from product architecture optimisation can and do outpace those of semiconductor upgrades.

In the post Moore's law world, architecture matters, hardware optimisation matters, doing custom ASICs are not just feasible, but a necessary option for many System Companies and OEMs.

As process technology nodes advance and Moore's Law slows at the leading edge, falling costs and increasing capacity on more mature nodes, coupled with the availability of high performance RF and mixed-signal IP is enabling a new paradigm in hardware and product innovation. OEMs can now embark on custom ASIC developments to take advantage of higher levels of integration, realising significant BOM savings.

While the open hardware movement, and open compute projects are still niche areas and for now custom ASICs are maybe out of reach, other megatrends like IoT are driving new platforms, architectures and opportunities. Not in over 30 years, have custom, mixed-signal, ASIC developments been within reach of so many lower volume hardware applications.

About the author
Donnacha O'Riordan is the director of services strategy for S3 Group.

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