Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Intel recommends 2.5D, 3D integration for next-gen chips

Posted: 06 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? 3D IC? heterogeneous integration? ISSCC? SoC?

Semiconductor manufacturing is headed towards another transformation. As revealed during the recent ISSCC, Intel presented the following slide. Quoting from Extremetech coverage: "At 10nm and below, the path forward will become increasingly murky.

What Intel has proposed is essentially a move towards other types of cost-saving technologies and process adoptions rather than relying on strict lithography improvement. Intel may be keeping its next-generation materials and lithography plans quiet, but the company does intend to push the envelope in other ways. 2.5D and 3D integration will be critical to the development of next-generation SoCs."

Moore's Law challenges below 10nm

We clearly agree with Intel that the heterogeneous integration enabled by 3D IC is an "increasingly important part of scaling." This will become even truer as mobile and Internet of Things (IoT) markets increasingly will consume the lion share of the semiconductor business.

With respect to "Poor for Low Cost," this is only true for the TSV approach to 3D ICs. The following slide was presented in the recent 3D ASIP (2014) conference as the summary of "Will the Cost of 3D ICs Ever Be Low Enough for High Volume Products" presentation by Chest Palesko, a leading market researcher:

3D IC cost for high volume products

So, yes TSV-based 3D IC is "Poor for Low Cost."

But the other form of 3D IC, the Monolithic 3D, is the lowest cost path for future scaling!

1???2???3???4?Next Page?Last Page

Article Comments - Intel recommends 2.5D, 3D integratio...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top