Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Implementation system from Cadence boosts turnaround time

Posted: 12 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design Systems? physical implementation? Spreadtrum? Renesas? Juniper Networks?

Cadence Design Systems Inc. has introduced its next-generation physical implementation solution that allows SoC developers to develop designs with industry-leading power, performance and area (PPA) while reducing time to market. Driven by a massively parallel architecture with breakthrough optimisation technologies, the Innovus Implementation System offers typically 10 to 20 per cent better PPA and up to 10X full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes, claimed the company.

According to the company, the Innovus Implementation System was designed with several key capabilities to help physical design engineers achieve best-in-class performance while designing for a set power/area budget or realise maximum power/area savings while optimising for a set target frequency.

The system flaunts a GigaPlace solver-based placement technology that is slack-driven and topology-/pin access-/colour-aware, enabling optimal pipeline placement, wirelength, utilisation and PPA, and providing the ideal starting point for optimisation, noted Cadence. In addition, it features advanced timing- and power-driven optimisation that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance.

Cadence also indicated that the Innovus Implementation System provides a unique concurrent clock and datapath optimisation that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power. Additionally, it delivers slack-driven routing with track-aware timing optimisation that tackles signal integrity early on and improves post-route correlation. A full-flow multi-objective technology also enables concurrent electrical and physical optimisation to avoid local optima, resulting in the most globally optimal PPA, noted the company.

The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place-and-route iteration. Its core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with eight to 16 CPUs. Likewise, the Innovus Implementation System features what Cadence describe as the industry's first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow improves turnaround time even with an increasing number of multi-mode, multi-corner scenarios.

1???2?Next Page?Last Page

Article Comments - Implementation system from Cadence b...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top