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Embedded flash IP boosts power efficiency of IoT, wearables

Posted: 16 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Faraday Technology? UMC? IoT? wearable? embedded flash?

Faraday Technology Corp., a ASIC/SoC and IP provider, and United Microelectronics Corp. (UMC), a global semiconductor foundry, have brought to market what they say is a complete set of low power consumption fundamental IPs geared for UMC's 55nm Low Power (LP) embedded flash process. According to the companies, the IPs are aimed to simultaneously meet both low-power and high-density requirements of Internet of Things (IoT) and wearable devices.

Low-power is prioritised for always-on devices in order to extend battery life. To fulfill the requirement, Faraday's memory compilers claim to significantly reduce power consumption in the standby mode by up to 70 per cent through optimisation of the low leakage memory periphery. The robust I/O cells are available for both digital and analogue interfaces, with a high voltage I/O cell option available that is especially compatible with a 5V interface. These IO cells are designed by using HVT core device to reduce leakage power. Furthermore, the IP suite also includes a low-power USB 2.0 OTG PHY with HVT core device, which significantly reduces power consumption in the idle mode by up to 65 per cent over traditional USB 2.0 OTG PHY.

"Faraday has been cooperating closely with UMC to build robust platform solutions for power-sensitive applications spanning from 0.18?m to 0.11?m, and now on 55nm eFlash," said Jensen Yen, associate VP of marketing and spokesperson at Faraday.

"UMC continues to broaden our strong IP portfolio to bring more low-power benefits to IoT chip designers," said Shih Chin Lin, senior director of IP development & design support division. "Our 55nmLP SST embedded flash technology is a widely adopted, mass production process that is supported by strong IP and design resources."

Faraday's complete IP set on 55nmLP SST embedded flash process includes the standard cell libraries, memory compilers, diffusion programmable ROM, Via ROM, I/O cells and low power USB 2.0 OTG PHY. The 3-series cell libraries, 7-track miniLib, 8-track generic libraries and 12-track UHS-Lib are all equipped with the low-power management of PSK cells and multi-Vt options, the companies added.

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