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Signal/power integrity device targets high-speed PCB design

Posted: 18 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mentor Graphics? signal integrity? power integrity? PCB design? DDR4?

Mentor Graphics Corp. has rolled out its most recent HyperLynx signal integrity/power integrity (SI/PI) product for high-speed PCB designs. According to the company, the solution addresses high-speed systems design challenges throughout the design flow, starting at the earliest architectural stages through post-layout verification, indicated the company.

The comprehensive HyperLynx SI/PI product provides tools for pre- and post-layout signal integrity, timing, crosstalk and power integrity analysis to quickly generate accurate simulation results to prevent design re-spins. Additional features in the HyperLynx SI/PI product include power-aware IBIS model support and the DDRx Wizard for DDR4/LPDDR4 (next-generation memory for low-power design) validation.

The latest HyperLynx tool supports IBIS [Input/Output Buffer Information Specifications] v5.0 models for ICs that represent non-ideal power effects. This capability accurately models supply currents, including pre-driver effects, switching slowdown due to sagging supply voltage, and better buffer capacitance modelling, stated Mentor. Power-aware IBIS modelling can be used in all simulation types including DDRx analysis, to study the power effects of timing and signal quality. This tool can model simultaneous switching noise (SSN), critical for designing next-generation memory interconnects.

HyperLynx SI/PI product

This screen capture illustrates the impact of the DQ (data lines) signal on power quality, and shows excellent correlation between traditional SPICE modeling and IBIS-based HyperLynx results.

Supporting the latest JEDEC standards, the DDRx Wizard verifies all DDR memory types, including DDR4 and its low-power (LPDDR4) counterparts. The DDRx Wizard can produce eye diagrams for complete verification of DDR3 and next-generation DDR4 memory systems. Each individual bit in the simulation is validated using eye-based metric checks, including integrated timing analysis for DDRx and LPDDRx.

Additional HyperLynx SI/PI product features include back drilling support for the accurate simulation of vias with appropriate stubs removed so that "what-if" scenarios can be quickly established, and drilling can be enabled or disabled. The Touchstone Viewer feature calculates ILD, ICR and other metrics in the IEEE 802.3 Ethernet specification and evaluates differential crosstalk characteristics for interconnects including S-parameter model conversion from standard to mixed mode. Additionally, SERDES enhancements are provided to support the latest IBIS 6.0 features, CTLE equalisation in FastEye Wizard, 128b/130b encoding and configuration file for batch AMI runs.

The HyperLynx product family for "power-aware" high-speed design is available.

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