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Understanding design compilation in hardware emulators

Posted: 26 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:emulators? software simulator? hardware? compilation? verification?

Not all emulators are created equal. There are differences in the maximum design capacity of a software simulator versus that of a hardware emulator.

In this post, I focus on the compilation process in hardware emulators. Likewise, the design capacity in hardware emulators, also the compilation flow, is heavily dependent on the type of technology used in the verification engine. At this time, each of the three hardware emulation vendors has embraced its own architecture:
???Cadence: Processor-based architecture
???Mentor: Custom-FPGA-based or emulator-on-chip architecture
???Synopsys: Commercial FPGA-based architecture

The first two are based on custom chips; the third is built using arrays of commercial FPGAs. The compilation process is different, and unique to each architecture.

Let's briefly recall the basics of a software compiler. A software compiler is a computer program or, better, a set of programs that transforms source code written in a programming language into an executable program made up of a sequence of instructions in the form of object code. The main operations performed by a compiler include lexical analysis, syntax analysis, semantic analysis, code optimisation and code generation.

Compilation in software simulators
A simulator is essentially a software algorithm running on a computer. The algorithm processes data representing a design model described in a design language at one of multiple hierarchical levels as illustrated in table 1.

Table 1: The design hierarchical levels each have corresponding description languages.

The compiler converts the design model into that data structure, following the guidelines of a software compiler, with some differences.

Hardware compilation
When the output of a compiler targets computer hardware at a very low level, for example, an FPGA or a structured ASIC, it is a hardware compiler because the source code produced effectively controls the final configuration of the hardware and its operations. The output of the compiler is not a sequence of instructions. Rather, it is an interconnection of transistors or lookup tables. A quintessential example is the compiler of a hardware emulator.

Compiler in processor-based emulators
The operation of a processor-based emulator vaguely resembles that of a software simulator. In both engines, the design-under-test (DUT) model is converted in a data structure stored in memory. In the case of the emulator, the design data structure is processed by a computing engine implemented in a vast array of Boolean processors, which gives the name to the emulator type.

Typically, the vast array is made up by relatively simple 4-input ALUs, possibly reaching into the millions in fully expanded configurations. These processors are tasked with evaluating all logic (Boolean) functions in the DUT in a time order controlled by a sequencer.

The principle of the operation is exemplified in the following figure 1 and table 2 using an oversimplified approach.

All operations are scheduled in time steps and assigned to the processors according to a set of rules to preserve the functional integrity of the DUT.

Figure 1: The logic functions in the DUT are in a time order controlled by a sequencer.

Table 2: An emulator's processors are tasked with evaluating functions in the DUT in a time order controlled by a sequencer.


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