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ASIP Designer tool cuts design time for ASIC processors

Posted: 27 Mar 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? ASIC? SDK? ASIP? base station?

Synopsys Inc. has unleashed its ASIP Designer tool that promises to accelerate the design of application-specific instruction-set processors (ASIPs) as well as programmable accelerators. The ASIP Designer's language-based approach allows the automatic generation of synthesisable RTL and software development kits (SDKs) from a single input specification, speeding the processor design and verification effort by up to five times compared to traditional manual approaches, stated the company.

"Using Synopsys' ASIP tools we've developed and deployed a full line of highly differentiated AudioSmart products. These products are based on the Conexant Audio Processing Engine, or CAPE, a Conexant-designed DSP," said Saleel Awsare, VP and GM at Conexant. "Application-specific architecture optimisations make CAPE highly efficient for far-field voice and audio playback processing, and Synopsys' tools assure ease of creation and programmability. By continuing to invest in ASIP tool technology, Synopsys is helping Conexant create market-leading domain-specific products."

ASIPs are deployed in various signal-processing intensive applications such as wireless base stations, mobile handsets, audio processing, image processing and cloud computing.

ASIP Designer enables users to explore multiple processor architecture alternatives in minutes, stated Synopsys. Using a single input specification in the nML language, the tool automatically generates both the synthesisable RTL of the processor as well as an SDK that includes an optimising C/C++ compiler, instruction set simulator, linker, assembler, software debugger and profiler. This ensures consistency of the hardware and the SDK at all stages of the design process.

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