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Less is more: Integrated RF-SOI faces new challenge

Posted: 06 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:RF-SOI? wafers? CMOS? RF switches? LTE?

Believe it: The industry will ship more than 1 million RF-SOI wafers this year and the annual growth rate is in the range of 35 per cent, leaving no doubt that RF-SOI is now mainstream and the most effective way to produce RF switches. In fact, the RF-SOI challenge is no longer simply to beat traditional JFET GaAs and Silicon-on-Sapphire (SoS) processes in performance and cost. That's done. Now, the goal is to use RF-SOI's performance to fit cellular 4G and 4.5G requirements without additional transmit filters that induce extra cost and insertion loss.

The RF-SOI core process starts from a mature CMOS process where a high-resistivity substrate (3000 x cm) replaces the standard bulk substrate (10 x cm resistivity). Starting from CMOS it delivers big benefits to RF-SOI over GaAs: the wafer cost is roughly cut in half and enables the possibility to integrate some digital content (like MiPI interfaces). Onto this high-resistivity substrate, a thin oxide layer is deposited to avoid latch-up issues which reduces the coupling between the devices and greatly increases the RF switch isolation (when Off).

Still, several technical challenges stand in the way of cellular 4G and 4.5G success: one is balancing insertion loss (IL) and isolation. The merit factor (R on , Coff), has to be as low as possible and most silicon suppliers target Ron * Coff close to 100 fs. The switch complexity has dramatically increased and today, a DP20T (two inputs, 20 outputs) is very popular; the target is to get IL

Switching

The switch complexity has dramatically increased. The target today is to get IL

Another challenge is to minimise transmit harmonic levels (H2 and H3) that generate severe receive desensitisation issues for some of the LTE carrier aggregation combinations. For example, a cellular phone transmitting in a low-band frequency on the primary LTE carrier and simultaneously receiving at high frequency on the secondary LTE carrier, may see leakage of the transmit harmonics generated by the RF antenna switch greater than the receiver sensitivity at the input of the high-band Rx path, desensitising the high-band receiver. To avoid additional filtering on the low-band Tx path, the RF-SOI switch must transmit H2 and H3 harmonics lower than -95 dBm, a challenging target.

Power Application

RF-SOI processes support "smart" and reconfigurable power amplifiers that introduce a lot of flexibility with and switching.

For Power Amplifiers (PA), and even between cellular and WLAN PAs, the challenge is different. With a cellular PA, RF-SOI processes allow the efficient combination of the switch and PA functions. Additionally, these processes support "smart" and reconfigurable PAs that introduce a lot of flexibility with band switching while also improving performance using an optimised matching network that is tuned regularly. Moreover, the use of specific nLDEMOS (N-type lateral drain extended metal oxide semiconductor) device has enabled the realization of excellent performance including power added efficiency (PAE) > 80 per cent at 2GHz, which is much better than can be achieved with CMOS bulk. If the RF-SOI process includes an nLDEMOS device, such as the H9SOI_FEM process technology of STMicroelectronics, it would also be more reliable, since the use of nLDEMOS makes handling more than 13V easier and more secure.


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