Future of 3D SoCs: Adding unlimited layers sans TSVs

The future of three-dimensional (3D) very large scale integration (VLSI) for system-on-chips (SoCs) will no longer involve through-silicon-vias (TSVs). Instead, the SoCs will be built on a single layered die, according to Karim Arabi, vice president of engineering at Qualcomm speaking at the International Symposium on Physical Design (ISPD-2015, Mar. 29-April 1).

"Our 3D VLSI technology, which we call 3DV, enables die size to be shrunk in half, while simultaneously increasing yields," Arabi told EE Times.

Qualcomm's motivation, according to Arabi, is market share in the 18 billion smartphones that he predicts will be produced by 2018—"more than all the computers and other electronic devices combined," he told us. He also noted that even though the cloud is offloading some computationally intensive applications—such as speech recognition—there will still be an increasing need for local processing power for most smartphone functions.

Qualcomm's not the only one pushing for an alternative. Recently, Intel proposed a move towards other types of cost-saving technologies and process adoptions. According to an ExtremeTech report, 2.5D and 3D integration will be critical to the development of next-generation SoCs.

In the long term, Qualcomm is building neural processing units (NPUs) modelled on the human brain, "because they are highly flexible and highly efficient for the next generation of mobile devices, cloud computing, Big Data processing, deep learning and machine learning," Arabi told us. But for the near term, Qualcomm is extending the capabilities of its already popular SoCs with its new type of 3DV interconnection and process technology.

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