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ACM announces IC physical design contest winners

Posted: 08 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Mentor Graphics? IC design? ACM? ISPD? place-and-route tool?

The Association of Computing Machinery (ACM) conducts an annual International Symposium on Physical Design (ISPD) that showcases the next-generation in the physical design of ICs. Each year a student contest is held to drive modern IC design, and was won this year by the National Taiwan University. This year, Kurt Antreich was also honoured for his outstanding achievements in electronic design automation (EDA).

The contest was organised by Ismail Bustany, chief technologist at Mentor Graphics, along with help from lead and senior engineers David Chinnery, Joseph Shinnerl, Vladimir Yutsis, Clive Ellis, Igor Gambarin and John Jones, and with strong support from Shankar Krishnamoorthy, chief scientist and head of R&D of the IC implementation division, Mentor Graphics.

Mentor Graphics sponsored contest

Results for all 20 phases of the Mentor Graphics sponsored contest were evaluated with its Olympus-SoC place-and-route tool. (Source: ISPD)

The ISPD-2015 contest, titled "Detailed Routing-Driven Placement with Fence Regions and Routing Blockages" addressed the problem of too rapid growth in the complexity of design rules as smaller process technologies have significantly increased "miscorrelation" between global routing and detailed routing. Traditional placement approaches that only use global routing congestion estimates are inadequate to meet the challenge.

The 2015 ISPD contest continued the work of the 2014 contest addressing this miscorrelation by scoring the routability and wire length of the placements using Mentor Graphic's Olympus-SoC detailed place-and-route tool.

Mentor Graphics supplied a web interface so that contestants from around the world could submit placements, then get detailed feedback, including images, of their routing approaches and solutions. In addition to the ISPD 2014 benchmark suites for sub-45nm design rules, including edge-type, minimum spacing, end-of-line, power/ground mesh, routing blockages, and rectilinear pin shapes, the 2015 benchmark extended the contest to include real industrial designs considerations.

For instance, rectilinear fence regions depicted voltage region placement constraints, in which only specified cells were allowed. And disconnected regions proved especially challenging for the contestants. Limits on standard-cell area utilisation were also imposed in order to reserve space for cell sizing and buffer insertion, as is typical in a place-and-route flow today, according to Mentor Graphics. Finally, macros with routing blockages and narrow placement channels were added to model top-level design features that are more challenging to place-and-route since placeable area is fragmented requiring long interconnects and blockage-aware routing models.

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