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Synopsys debuts PHY IPs for TSMC's 16nm FinFET Plus process

Posted: 09 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? FinFET? TSMC? SoC design?

Synopsys Inc. has unleashed a line-up of DesignWare PHY IP for TSMC's 16nm FinFET Plus (16FF+) processes, allowing designers to integrate required functionality in mobile and enterprise SoCs with less risk. The silicon success of the DesignWare IP in TSMC's 16FF+GL and 16FF+LL processes enables designers to accelerate the development of SoCs that incorporate embedded memories and interface IP for USB 3.0, 2.0 and HSIC; PCI Express 4.0, 3.0 and 2.0; SATA 6G; HDMI 2.0; MIPI D-PHY; DDR4/3 and LPDDR4/3/2 protocols on TSMC 16FF+ processes, detailed the company.

The DesignWare STAR Memory System product is a comprehensive, integrated test, repair and diagnostics solution that supports Synopsys and third-party embedded memories. TSMC uses DesignWare STAR Memory System to characterise all of its 16FF+ memory compilers. The optimised test and repair algorithms maximise test coverage while reducing test time, lowering test cost and improving manufacturing yield.

DesignWare PHY IP portfolio

Silicon-proven DesignWare PHY IP, designed for high quality and reliability, offers excellent performance margins on TSMC 16FF+ processes.

Synopsys also provides DesignWare Logic Libraries for the TSMC 16FF+ processes that include 7.5-, 9- and 10.5-track libraries, power optimisation kits and high performance core (HPC) kits. All Synopsys embedded memories and logic libraries, including those on TSMC 16FF+ processes, work seamlessly with the IC Compiler II place-and-route system that accelerates throughput and improves quality of results.

The DesignWare USB 3.0 and 2.0, 16G PHY, PCI Express 4.0, 3.0 and 2.0, SATA 6G, HDMI 2.0, MIPI D-PHY, DDR4 multiPHY (including DDR4/3 and LPDDR4/3/2), logic library and embedded memory IP for TSMC's 16FF+ process, as well as STAR Memory System and IC Compiler II, are available.





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