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How to characterize GaN power devices

Posted: 17 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Power gallium-nitride? GaN? RF? FETs? waveform monitoring?

Power gallium-nitride (GaN) devices are an exciting addition to the power designer's tool box. This is true specifically where there is a desire to explore how GaN's higher switching frequencies can lead to higher efficiencies and higher power densities. RF GaN is a proven technology in high-volume production for power amplifiers used in cellular base stations and several military/aerospace systems due to its advantages over silicon. In this article, we compare the degradation mechanisms of GaN FETs with silicon FETs and discuss the need for waveform monitoring.

Lifetime predictors
Power GaN has lagged RF GaN because of the time required to implement cost-reduction strategies used by multiple suppliers. Most notably is the move to 6-inch silicon substrates and lower cost plastic packaging. It is important for power designers to understand performance improvement promises of GaN, as well as some of the degradation mechanisms that can affect the performance of the final product over time.

Joint Electron Device Engineering Council (JEDEC) qualification standards for silicon have proven to be good predictors for product lifetimes, but there is no equivalent standard for GaN today. To mitigate the risk of using new technologies, it is prudent to look at the specific-use case and environmental limits where the new technology is to be applied and build up prototypes that can be stressed and monitored for change. Real-time monitoring of a large number of prototypes poses some interesting engineering challenges, especially when GaN device voltages can approach 1000V and have dv/dts greater than 200 V/ns.

One commonly used graph to determine whether a power FET can meet the intended use case is the safe operation area (SOA) curve. One example is shown in figure 1.

Figure 1: Example of a GaN FET SOA curve with Rds-On = 100 milliohm.

Hard-switched designs
Power GaN FETs are used in both hard-switched and multi-megahertz resonant designs. Either zero-voltage (ZVS) or zero-current (ZCS) topologies are being demonstrated above several kilowatts. The most stressed region of the SOA curve is at the highest voltage and highest current area in the upper right. Operating a power GaN FET in this hard-switched area causes increased stress due to several mechanisms. The easiest to understand is thermal stress. For example, with an inductive switching test circuit, it is possible to cause the device to switch from approximately zero current when OFF, with a voltage of several hundred volts on the drain, to almost instantly a current of 10 amps when ON.

The voltage across the device times the current through it is the instantaneous power dissipation, which for this example, could be >500 Watts in the middle of the transition. For a typical power GaN device size of 5 mm x 2 mm, this would be 50W per mm2. It should come as no surprise that the SOA curve shows that only short pulses can be supported for operation in this area. The upper right hand of the SOA curve is seen to be a function of pulse-width due to the device's thermal limitations and packaging. Shorter pulses cause less heating due to the thermal time constant as seen in the curves. Enhanced package technology can be used to reduce thermal impedance from the junction case from ~15C/W to as low as 1.2C/W. This can expand the SOA due to reduced device heating.

SOA curve
Texas Instruments has a family of standard-footprint power MOSFETs, DualCool and NexFETs. These MOSFETs dissipate heat through the top and bottom of their packages and can provide 50 per cent more current than traditional footprint packages. This gives designers the flexibility to use higher currents without increasing end equipment size. A big advantage of GaN FETs is the very short switching times achievable versus silicon FETs. Additionally, reduced capacitance and the absence of Qrr lead to much lower switching losses. The integral of the voltage times the current, as the device switches, is the amount of power that the device must dissipate. Lower losses result in lower device temperatures and expanded SOA.

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