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FPGA prototyping of SoC designs

Posted: 13 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? prototyping? ESL? system-on-chip? SoC?

Today's off-the-shelf FPGA prototyping systems have established their value in every stage of the system-on-chip (SoC) design flow. Moving beyond traditional applications such as in-circuit testing and early software development, this technology has expanded to encompass functional design and verification (see also Expanding the role of FPGA prototypes).

FPGA-based prototypes work with electronic system level (ESL) design environments to refine, validate, and implement the chip's architecture, and with simulation tools to achieve an order of magnitude (or more) increase in verification speed.

There are several drivers of this technology: the need to quickly construct high-performance prototypes; the demands of growing design size and complexity (see also Advances in FPGA-based prototyping); and the need to utilise prototypes as an enterprise-wide resource. Globalisation has replaced localized design teams with teams that are geographically-distributed. Consequently, FPGA prototyping solutions must now provide network access and remote management capabilities coupled with the ability to expand resources such as memory or add-on components. This allows realising multiple hardware and software implementations for numerous, geographically-dispersed teams.

The FPGA prototyping system must offer enterprise-wide accessibility!a complete prototyping platform is one that operates at any functional design stage, with any design size, and across multiple geographical locations. All of these capabilities must be available on-demand and be remotely-accessible at all times. Such an approach significantly increases engineering productivity and reduces the end-product's time to market, while increasing its return on investment (ROI), as well as increasing the lifetime ROI of the FPGA prototyping platform itself.

Growing SoC design challenges
SoC size and complexity are increasing at an exponential rate. According to a keynote presentation by Gary Smith at the International Technology Roadmap for Semiconductors Conference in 2013, potentially available SoC gate counts will quadruple from 420 million in 2014 to 1.68 billion in 2020. International Business Strategies (IBS) reported that software development and hardware verification are the two leading factors in total SoC design cost (figure).

Figure: Software development and hardware verification are the predominant factors in SoC design cost (source: IBS).

These software- and complexity-driven cost and effort increases are accompanied by an elevated risk of late delivery, and even the possibility of outright failure. Cost and risk are generally mitigated by the extensive use and reuse of intellectual property (IP)!both silicon and software!but the complete silicon/software design must nonetheless be prototyped and tested as a whole.

FPGA-based prototyping solutions: Addressing today's needs

For an FPGA prototype to meet the requirements of this "whole design", it must address the following criteria:
???User access
???Compile/partition efficiency
???System interface capability
???Analysis and debug capability
???Application throughout the functional design flow

Utility of current FPGA-based prototyping systems
The key criteria for evaluating the utility of an FPGA-based prototyping system are as follows:

1. Access to FPGA prototyping systems must not be constrained by the use of localized systems that require local management and control. Limited access can present a significant hindrance to modern SoC design teams!especially software development teams!which are often globally distributed.

2. The compile and build environment must incorporate important features such as the ability to partition a design automatically and/or with user guidance; automatic pin-multiplexing insertion and clock analysis. Also important are a convenient user interface to FPGA-specific place-and-route (P&R) tools allowing for quick flow turnaround for changes and ECOs.

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