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Cypress 4Mb asynchronous SRAMs promise data reliability

Posted: 23 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress Semiconductor? asynchronous SRAM? data reliability?

Cypress Semiconductor Corp. has started sampling its 4Mb asynchronous SRAMs with on-chip error-correcting code (ECC) feature. Aimed to simplify designs and cut board space, the devices guarantee data reliability in various industrial, military, communication, data processing, medical, consumer and automotive applications, without the need for additional error correction chips.

Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress' asynchronous SRAM family performs all error correction functions inline, without user intervention, delivering best-in-class soft error rate (SER) performance of less than 0.1FIT/Mb (one FIT is equivalent to one error per billion hours of device operation). The devices are pin-compatible with current asynchronous fast and low-power SRAMs, enabling customers to boost system reliability while retaining board layout. The 4Mb SRAMs also include an optional error indication signal that indicates the correction of single-bit errors.

4Mb asynchronous SRAM

The Cypress 4Mb asynchronous SRAMs are available in three options, Fast, MoBL and Fast with PowerSnooze, an additional power-saving deep sleep mode that achieves 15A (max) deep-sleep current for the 4Mb SRAM. Each of the options is offered in industry standard x8 and x16 configurations. The devices operate at multiple voltages (1.8V, 3V and 5V) over -40C to 85C (Industrial) and -40C to 125C (Automotive-E) temperature ranges.

The SRAMs are sampling in industrial temperature grade, with production expected in July 2015. These devices will be available in RoHS-compliant 32-pin SOIC, 32-pin TSOP II, 36-pin SOJ, 44-pin SOJ, 44-pin TSOP II and 48-ball VFBGA packages.

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