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Verilog-AMS vs SPICE view for SoC verification

Posted: 27 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:IP? SoCs? Analogue Mixed Signal? AMS? simulation?

Dozens of analogue and digital IP blocks are incorporated into today's SoCs. They contain multiple voltage domains that support several modes, like Standby, Low power, Reduced Clock Mode, etc. Additionally, there are several IPs used to interface with real world signals and external ICs. These include Data Converters, Clock sources like RC Oscillators and Crystal Oscillators, PLLs, etc.

To achieve first pass success of such complex SoCs in silicon, a robust pre-silicon verification methodology needs to be implemented. The high level of analogue IPs in these SoCs necessitates the need for analogue mixed signal (AMS) simulations that target the various features and modes being supported. In addition, many of these simulations also need to be run across process and temperature corners. This results in an AMS simulation count that runs into the hundreds. Defining and implementing these simulations accurately is a complex task. Moreover, simulating all of them is quite computationally intensive.

Thus it is important to weigh the pros and cons of a Verilog/Verilog-AMS view versus a SPICE view for all the analogue blocks and IPs within a SoC. This process needs to be carefully repeated for different AMS simulations, each targeting a different type of check. Verilog/Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. In this paper we comparatively analyse the usage of both the views from a perspective of Data Converters and Clocking IPs in a SoC.

This article is a logical continuation of our previous post, Verilog-AMS vs SPICE view for power management.

Data converter: Static and dynamic functionality and contention check

We hear of the words 'Analogue' and 'Digital' very often; and mostly we hear how 'Digital' is better that 'Analogue' in many ways. But does this mean we can do away with all Analogue circuitry on our SoC? Not quite!

Real world signals are all continuous time continuous value signals. The SoCs produced by the industry serve a variety of purposes: Drive an LCD panel, or perform motor control, or act on the data provided by sensors, or drive 5-channel audio speakers, etc. Thus we see a crucial need to translate real world signals to a discrete time discrete value digital value, and vice versa. This operation is performed by Data Converters. Examples include Analogue to Digital Converters, Digital to Analogue Converters, etc.

Such data converters are made up of an Analogue hard-block along with a digital configuration block. The signal path involving Data Converters in a SoC-AMS setup also include the Input/Output PADs (I/Os), and a set of Analogue Multiplexers through which the analogue signals are routed from OR to the external world.

The digital configuration block of Data Convertor, is synthesised logic and can be safely taken in Verilog/VAMS without loss in accuracy. For a basic sanity test from an integration point of view, the PADs can be taken in VAMS view, which would also give a high level of accuracy. This would also permit modelling of basic contention like weak/strong pull-up/pull-down, since strength of drivers can be modelled accurately using VAMS. Similarly since the targeted check is simply the integration and conversion check of slow varying analogue signals, the ADC analogue block too can be in VAMS.

Figure 1: On Chip DAC can be used for testing multiple analogue blocks.

VAMS views can also be taken in AMS simulations where the Data Convertor is just one the components of the sub-system being verified. For example the output voltage of a Digital to Analogue Convertor (DAC) is used to verify other analogue blocks such as voltage comparators. Here the whole sub-system is under verification and analogue voltages can be driven based on a digital look up table modelled inside DAC VAMS view. This will save overall simulation time of sub-system under verification and improve the coverage as well.

But on the other hand, modelling of static & dynamic parameters of data converters in VAMS view will not be feasible. These parameters include comparator offset, integrated non-linearity (INL), differential non-linearity (DNL), Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio (SNDR), Total Harmonic Distortion (THD), etc. These parameters can be accurately simulated only when the Data Convertor analogue block is in SPICE.

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