Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

Exploring the failure analysis process

Posted: 28 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:failure analysis? DC-DC converter? transistor? PCB? thermal imaging?

Finding and fixing problems has become increasingly challenging as semiconductor processes enable more compact, lower-power devices created from smaller structures. A device that might appear to have been correctly manufactured can still show performance problems thanks to defects arising from a single atom being in the wrong place. Determining the root cause of these failures requires a disciplined and systematic analytical process, along with sophisticated tools for testing and visualizing the behaviours and other characteristics of sample devices.

The failure analysis process
Today's failure analysts require a broad knowledge of the materials, metals and chemistry used to create semiconductors, as well as detailed information about devices' underlying architectures, how they are expected to function, and the types of failures likely to occur. Analysts start with the broadest possible system view and narrow the investigation to the underlying failure mechanism, whether it is on a board, in a component, or far deeper in the device, whether in a logic block, DC-DC converter, or even a transistor.

The failure analysis process is generally divided into two phases: non-destructive and destructive (figure 1). Clearly, the first analytical steps should be non-destructive including electrical test and characterisation. That's why the non-destructive and destructive phases are alternatively referred to as electrical and physical analysis, respectively. During the second, destructive phase, even de-capping a part exposes the device to chemical and temperature changes would could not only damage the part, but potentially compromise the failure signature as well.

Figure 1: The failure analysis process begins with non-destructive tests to evaluate package integrity and obtain an electrical failure signature. The process then moves on to destructive techniques to localise and diagnose the problem.

After acquiring the failure signature, failure analysts can take a number of steps for deeper investigation. The analysis starts at the board level to acquire the electrical data necessary to localise failures to a PCB or component. From there, analysis can continue to the component level for IC and discrete component analysis while the analyst looks for the root causes of the failure. A meta-loop process is used to test each failure hypothesis, obtain evidence to either confirm or disprove it, and gather more information, if necessary. The evidence can then be used to propose a new hypothesis. Applying short-loop techniques repeatedly throughout the analysis will deliver the underlying failure mechanism.

Tools of the trade
The tools for non-destructive testing include external visual examination, x-ray and C-mode scanning acoustic microscopy (CSAM), and time domain reflectometry (TDR). TDR lets an analyst identify opens and shorts on pins and decide if a defect is in the package or at the interface to the die. Magnetic techniques that take advantage of superconducting quantum interference device (SQUID) and GMR (giant magneto resistive) microscopy are good for finding leaks and shorts, and for mapping their locations on the current path. Hot spots can also be identified and mapped using thermal imaging that provides actual temperature measurements. Additionally, non-destructive tests are also available for evaluating package issues, including PIND (particle impact noise detection) for cavity packages, and fine and gross leak for hermetic packages.

One of the most commonly used electrical tests is curve trace, which involves sweeping voltage and current to create an IV plot. This test reveals opens and shorts as well as resistance and leakage and helps to verify and visualise the electrical failure signature. Often, a device that may have been categorised as a functional failure will be re-labelled a parametric failure through the observation of an abnormal pin-to-pin curve trace across the power supply. Figure 2 illustrates a typical curve trace on a device with a defective pin. The curve has shifted to show where the leakage is occurring and providing important evidence for establishing the next steps in the analysis.

Figure 2: On a typical I/O pin, the curve trace displays the forward-biased ESD protection diodes. In other cases a power supply (VDD) to ground (GND) anomalous curve can reclassify a functional failure as a parametric failure.


1???2???3?Next Page?Last Page



Article Comments - Exploring the failure analysis proce...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top