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Exploring the failure analysis process

Posted: 28 Apr 2015 ?? ?Print Version ?Bookmark and Share

Keywords:failure analysis? DC-DC converter? transistor? PCB? thermal imaging?

Once an electrical failure signature has been acquired through non-destructive testing, the next step is localisation, ideally to within a few microns of the exact location if the problem is very deep in the device.

The first step is to perform internal visual inspection using optical microscopy. This is an important tool for looking at the bond wires, the die attach, big cracks in the die, electrical overstress, corrosion, and other large elements. While techniques including light microscope illumination can improve the capabilities of this tool, transistors and any items of 90 nm or less in size are generally too small for this level of visualisation.

Another important technique that can be used either from the die front side or back side is IR (infrared) thermography for hot spot detection. These microscopes measure true temperature with pixel-by-pixel emissivity correction, imaging heat at a 3 micron infrared wavelength and creating a colour-coded temperature map or hot spot overlay image. Power modulation coupled with averaging techniques can be used to increase hot spot detection sensitivity. Another modulation technique called lock-in/pulse sampling can similarly improve effectiveness through the use of bi-level power modulation and bi-mode logic state modulation.

Figure 3 shows two examples where power was being dissipated in the sample and creating a hot spots. Temperature rise is dependent on the power dissipated per unit area, so in this case it was very easy to see where the device was getting hot.

Figure 3: The top infrared thermography image shows the temperature gradient across the die. The bottom image shows the location of a gate oxide breakdown site.

If the same 100 mA were, however, entering an entire logic block, the heat would be spread out over larger area, the temperature rise would be much lower, and the hot spot would be more difficult to see. While it might take higher power and current to see this type of problem with infrared thermography, the technique nevertheless is very good for asking the basic question of how hot the sample area is. This can be important for devices like RF output transistors that must be very reliable, and devices that need to be put into power-down sleep mode. Infrared thermography can tell the analyst how hot the area is, whether it is still drawing current during sleep mode, and the location in the logic block of the defect that is causing the problem.

Thermal imaging can only go so far, though. It is very difficult, for instance, to localise shorts in a power supply node, which is like a large metal mesh spanning the entire surface of the chip. Many things can be masked by the metal. This is where magnetic imaging tools like SQUID microscopes can be important, used either from the front or back side of the die.

Employing parallel yttrium barium copper oxide (YBCO) Josephson junctions operated at 68-72K, these tools can provide analysts with another way to map the current path into the device and trace where a problem might exist. Electrons tunnelling through the junctions undergo phase interference that is dependent on magnetic field strength. This phenomenon enables analysts to observe a very high peak of magnetic field where the current density is high, bringing the investigation to within a few microns of the location so that further physical analysis can be conducted.

For some devices, like flip-chips, the only available visualisation technique is light emission microscopy, also known as EMMI. It can be used from either the front or back side and often without die thinning. This highly efficient optical analysis technique is used to detect defects or abnormal operation of semiconductor devices based on the photons of light they emit in the visible and near infrared (IR) spectrum. These defect-related photon emissions are generally associated with forward or reverse biased p-n junctions, transistors in saturation, latch-up, and gate oxide breakdown. In the example of forward-biased p-n junctions, the devices' emission is generated by placing a large number of electrons and holes in close physical proximity where they recombine and generate light with spectra centred around the silicon bandgap. This light can be captured with a sensitive charge-coupled device (CCD) or (InGaAs indium gallium arsenide) camera in a light-tight box. Two images are captured, one with the microscope light off, the next with power applied to see the source of the emission (figure 4).

Figure 4: Emission microscopy localizes failures non-destructively and other than decapsulation requires little in the way of sample preparation.

Front side emission>As figure 5 shows, latch-ups in particular shine very brightly using this technique. Regardless of device type, any transistor under normal operation will generate a small amount of light. All light emission sites are overlaid on a background die image, enabling analysts to localise failures in relation to circuit features.

Figure 5: Backside emission imaging during latch-up pinpoints to location of the failure.

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